firtool-1.139.0

What's Changed

• [FIRRTL][GrandCentral] Add -no-views option. by @dtzSiFive in #9304
• [FIRRTL] Remove -allow-adding-ports-on-public-modules. by @dtzSiFive in #9301
• [verif] Add canonicalizers of clocked assertlikes by @seldridge in #9307
• [ESI] Include more WindowType info in manifest by @teqdruid in #9308
• Bump LLVM by @uenoku in #9306
• [FIRRTL] Use type inference for domain anon op by @rwy7 in #9312
• Document Copilot build setup (incl. PyCDE/ESI) and align integration image defaults by @Copilot in #9314
• [HW] Extend ElementType parsing to support union types by @yassinz in #9318
• [ESI][Runtime] Add non-list Window type read translations by @teqdruid in #9319
• [ESI][Runtime] Add non-list Window type write translations by @teqdruid in #9324
• [FIRRTL] Allow domain ports after associations by @seldridge in #9323
• [Verif] Add hw.constant Verif canonicalizers by @seldridge in #9325
• [ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. by @uenoku in #9309
• [FIRRTL] Remove nonlocal field from annotations when NLA becomes local by @uenoku in #9329
• [ESI][Runtime] Translate message performance enhancements by @teqdruid in #9330
• [ESI][Runtime] Port Python bindings from pybind11 to nanobind by @Copilot in #9322
• [Python][LLVM] Add LLVM dialect and modify export llvm ir test by @yassinz in #9316
• [FIRRTL] Don't create empty modules in LowerLayers by @seldridge in #9333
• [FIRRTL] Fix Dedup issue caused by name shadowing by @fabianschuiki in #9336
• [ESI][Runtime] Parallel encoded list translation support by @teqdruid in #9334
• [FIRRTL][Dedup] Improve error messages for nested bundle type mismatches by @uenoku in #9338
• [FIRRTL][firtool] Add --inline-input-only-modules option to firtool by @uenoku in #9332
• [ESI] Improve RpcServer/CosimBackend usability through distributed package by @mortbopet in #9339
• [ImportVerilog][MooreToCore] Added support for int_to_real by @KavyaChopra04 in #9317
• [Sim][MooreToCore] Added octal formatting specifier for printing integers by @KavyaChopra04 in #9343
• Reapply "[circt-lsp-server] Make time source injectable" by @uenoku in #9342
• [Python][Sim] Bind sim dialect to python by @teqdruid in #9345
• [MooreToCore] Added real_to_int support by @KavyaChopra04 in #9346
• [LLHD] Fix HoistSignals with non-uniform drive delays by @fabianschuiki in #9349
• [ImportVerilog] Fix class property segfault and emit error by @fabianschuiki in #9347
• [Datapath] Convert comparison operators to arithmetic - avoiding multiple carry propagate adders by @cowardsa in #9344
• [PyCDE] Emit $info messages by @teqdruid in #9351
• [ESI] Factor out gRPC/proto usage in Cosim backend by @mortbopet in #9350
• [MooreToCore] Support float comparison operations by @maerhart in #9355
• [Arc] Use explicit CompReg reset instead of mux by @TaoBi22 in #9359
• [RTG] Add virtual register reduction pattern by @maerhart in #9283
• [ImportVerilog][Moore] Use more specific casting operations for string, real, and time casts by @maerhart in #9352
• [arcilator] add option to treat async firreg resets as sync by @TaoBi22 in #9360
• [MooreToCore] Support binary real operations by @maerhart in #9362
• [ESI][RpcClient] Implement synchronization for RPC completion by @mortbopet in #9363
• [ImportVerilog] Convert realtime values to f64 before operations by @maerhart in #9364
• [ImportVerilog] Properly cast subroutine call result value by @maerhart in #9365
• [ImportVerilog] Cast func call arguments to types matching func decl by @maerhart in #9366
• [ImportVerilog] Add support for program definitions by @fabianschuiki in #9377
• [MooreToCore] Lower $time to new LLHD current time op by @fabianschuiki in #9378
• [Seq] Update HWMemSimImpl's replSeqMem to support higher latency. by @mikeurbach in #9383
• [CombToArith] Don't reject unknown ops by @pscabot in #9394
• [Docs] Add tools page to the website and circt-verilog docs by @cowardsa in #9385
• [Transforms][MapArithToComb] Added best-effort lowering for Arith to Comb by @KavyaChopra04 in #9380
• [Arc][SplitFuncs] Ignore extern func ops by @TaoBi22 in #9393
• [ImportVerilog] Add basic event type support by @fabianschuiki in #9381
• [ArithToComb] Avoid converting float constants to HW by @fabianschuiki in #9407
• [FSMToCore] Add FSMToCore pass by @TaoBi22 in #9354
• [ImportVerilog] Replace FormatTimeOp with FormatIntOp by @fabianschuiki in #9406
• [LLHD] Add conversion ops between time and integer values by @fabianschuiki in #9405
• [Sim][MooreToCore] Added width, alignment and padding support for moore.fmt.int by @KavyaChopra04 in #9390
• [Python] Build and upload Python 3.14 wheel. by @richardxia in #9399
• [HWToLLVM] Ignore operations of other dialects by @fzi-hielscher in #9412
• [circt-test] Add options to pick only formal/simulation tests by @fabianschuiki in #9411
• [circt-test] Add supported test kind to runner config by @fabianschuiki in #9410
• [ESI] Handle possible exception in RpcServer::SendToServer by @mortbopet in #9409
• [MooreToCore][Sim] Added support for moore.fmt.real by @KavyaChopra04 in #9397
• Fix isSeqMem() check to allow externalization of memories with read-/write-latency >= 1 by @trmckay in #9419
• [LLHD] Processes with timed waits are not combinational by @fabianschuiki in #9422
• [circt-test] Install test runners alongside circt-test by @fabianschuiki in #9413
• [circt-test] Add Verilator test runner by @fabianschuiki in #9414
• [HW] Add pass to convert bitcast operations by @fzi-hielscher in #9425
• [arcilator][HWToLLVM] Use HWConvertBitcasts pass in arcilator pipeline by @fzi-hielscher in #9426
• [CI] Set timeout to individual lit tests by @uenoku in #9424
• [circt-test] Reuse firtool pipeline to emit split verilog by @fabianschuiki in #9427
• [CombToLLVM] Add conversion for comb::ReverseOp to LLVM dialect by @yassinz in #9431

New Contributors

• @KavyaChopra04 made their first contribution in #9317
• @pscabot made their first contribution in #9394

Full Changelog: firtool-1.138.0...firtool-1.139.0