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[hw,rv_dm,rtl] Convert DMI to real TL-UL interface
Change DMI implementation to TL-UL, and rework rv_dm to match Ensure rv_dm continues to respond with zeroes when the DM is not present / inaccessible. Co-authored-by: Michael Schaffner <[email protected]> Co-authored-by: Alexander Williams <[email protected]> Signed-off-by: Robert Schilling <[email protected]>
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-95
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17 files changed

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‎hw/ip/rv_dm/data/rv_dm.hjson‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
{ protocol: "tlul", direction: "host", name: "sba" }
3131
{ protocol: "tlul", direction: "device", name: "regs" }
3232
{ protocol: "tlul", direction: "device", name: "mem" }
33+
{ protocol: "tlul", direction: "device", name: "dbg" }
3334
],
3435
scan: "true", // Enable `scanmode_i` port
3536
scan_reset: "true", // Enable `scan_rst_ni` port
@@ -108,26 +109,6 @@
108109
asserted when the hardware debug mechanisms are enabled in the system.
109110
'''
110111
},
111-
{
112-
struct: "tl_h2d"
113-
package: "tlul_pkg"
114-
type: "uni"
115-
name: "dmi_tl_h2d"
116-
act: "rcv"
117-
desc: '''
118-
TLUL-based DMI request input port
119-
'''
120-
}
121-
{
122-
struct: "tl_d2h"
123-
package: "tlul_pkg"
124-
type: "uni"
125-
name: "dmi_tl_d2h"
126-
act: "req"
127-
desc: '''
128-
TLUL-based DMI response output port
129-
'''
130-
}
131112
{ struct: "lc_tx"
132113
type: "uni"
133114
name: "lc_dft_en"
@@ -658,5 +639,18 @@
658639
}
659640
},
660641
]
642+
// Debug bus attachment
643+
dbg: [
644+
{ window: {
645+
name: "dbg"
646+
// 0x0 ... 0x40 word addresses are allocated here.
647+
items: "128"
648+
swaccess: "rw",
649+
data-intg-passthru: "true",
650+
byte-write: "false",
651+
desc: '''Access window to DM CSRs.'''
652+
}
653+
},
654+
]
661655
}
662656
}

‎hw/ip/rv_dm/doc/interfaces.md‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ All hardware interfaces of the debug system are documented in the [PULP RISC-V D
88
Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`rv_dm`** has the following hardware interfaces defined
99
- Primary Clock: **`clk_i`**
1010
- Other Clocks: **`clk_lc_i`**
11-
- Bus Device Interfaces (TL-UL): **`regs_tl_d`**, **`mem_tl_d`**
11+
- Bus Device Interfaces (TL-UL): **`regs_tl_d`**, **`mem_tl_d`**, **`dbg_tl_d`**
1212
- Bus Host Interfaces (TL-UL): **`sba_tl_h`**
1313
- Peripheral Pins for Chip IO: *none*
1414
- Interrupts: *none*
@@ -20,8 +20,6 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
2020
| next_dm_addr | rv_dm_pkg::next_dm_addr | uni | rcv | 1 | 32bit word address of the next debug module. Set to 0x0 if this is the last debug module in the chain. |
2121
| jtag | jtag_pkg::jtag | req_rsp | rsp | 1 | JTAG signals for the RISC-V TAP. |
2222
| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the hardware debug mechanisms are enabled in the system. |
23-
| dmi_tl_h2d | tlul_pkg::tl_h2d | uni | rcv | 1 | TLUL-based DMI request input port |
24-
| dmi_tl_d2h | tlul_pkg::tl_d2h | uni | req | 1 | TLUL-based DMI response output port |
2523
| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the DFT mechanisms are enabled in the system. |
2624
| pinmux_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from pinmux. This is a latched version of the lc_hw_debug_en signal and is only used to gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live while the rest of the system undergoes an NDM reset. |
2725
| otp_dis_rv_dm_late_debug | prim_mubi_pkg::mubi8 | uni | rcv | 1 | |
@@ -36,6 +34,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
3634
| sba_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
3735
| regs_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |
3836
| mem_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |
37+
| dbg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |
3938

4039
## Security Alerts
4140

‎hw/ip/rv_dm/doc/registers.md‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -863,5 +863,19 @@ Access window into the debug ROM.
863863
- Access: `ro`
864864
- Byte writes are *not* supported.
865865

866+
## Summary of the **`dbg`** interface's registers
867+
868+
| Name | Offset | Length | Description |
869+
|:--------------------|:---------|---------:|:--------------------------|
870+
| rv_dm.[`dbg`](#dbg) | 0x0 | 512 | Access window to DM CSRs. |
871+
872+
## dbg
873+
Access window to DM CSRs.
874+
875+
- Word Aligned Offset Range: `0x0`to`0x1fc`
876+
- Size (words): `128`
877+
- Access: `rw`
878+
- Byte writes are *not* supported.
879+
866880

867881
<!-- END CMDGEN -->

‎hw/ip/rv_dm/dv/sva/rv_dm_bind.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ module rv_dm_bind;
99
) tlul_assert_device_dmi (
1010
.clk_i,
1111
.rst_ni,
12-
.h2d (dmi_tl_h2d_i),
13-
.d2h (dmi_tl_d2h_o)
12+
.h2d (dbg_tl_d_i),
13+
.d2h (dbg_tl_d_o)
1414
);
1515

1616
bind rv_dm tlul_assert #(

‎hw/ip/rv_dm/dv/tb.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@ module tb;
2626
rv_dm_if rv_dm_if(.clk(clk), .rst_n(rst_n));
2727

2828
// Used for JTAG DTM connections via TL-UL.
29-
tlul_pkg::tl_h2d_t dmi_tl_h2d;
30-
tlul_pkg::tl_d2h_t dmi_tl_d2h;
29+
tlul_pkg::tl_h2d_t dbg_tl_h2d;
30+
tlul_pkg::tl_d2h_t dbg_tl_d2h;
3131

3232
`DV_ALERT_IF_CONNECT()
3333

@@ -43,11 +43,11 @@ module tb;
4343
.jtag_o ({jtag_if.tdo, jtag_tdo_oe}),
4444
.scan_rst_ni (rv_dm_if.scan_rst_n),
4545
.scanmode_i (rv_dm_if.scanmode),
46-
.tl_h2d_o (dmi_tl_h2d),
47-
.tl_d2h_i (dmi_tl_d2h)
46+
.tl_h2d_o (dbg_tl_h2d),
47+
.tl_d2h_i (dbg_tl_d2h)
4848
);
4949
`else
50-
assign dmi_tl_h2d = tlul_pkg::TL_H2D_DEFAULT;
50+
assign dbg_tl_h2d = tlul_pkg::TL_H2D_DEFAULT;
5151
`endif
5252

5353
// dut
@@ -100,8 +100,8 @@ module tb;
100100
.jtag_o ({jtag_if.tdo, jtag_tdo_oe}),
101101
`endif
102102

103-
.dmi_tl_h2d_i (dmi_tl_h2d),
104-
.dmi_tl_d2h_o (dmi_tl_d2h)
103+
.dbg_tl_d_i (dbg_tl_h2d),
104+
.dbg_tl_d_o (dbg_tl_d2h)
105105
);
106106

107107
// Apply the muxing that we get in rv_dm, where the JTAG interface that actually connects to the

‎hw/ip/rv_dm/rtl/rv_dm.sv‎

Lines changed: 30 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,8 @@ module rv_dm
7171
input jtag_pkg::jtag_req_t jtag_i,
7272
output jtag_pkg::jtag_rsp_t jtag_o,
7373
// TL-UL-based DMI
74-
input tlul_pkg::tl_h2d_t dmi_tl_h2d_i,
75-
output tlul_pkg::tl_d2h_t dmi_tl_d2h_o
74+
input tlul_pkg::tl_h2d_t dbg_tl_d_i,
75+
output tlul_pkg::tl_d2h_t dbg_tl_d_o
7676
);
7777

7878
///////////////////////////
@@ -114,7 +114,7 @@ module rv_dm
114114
tlul_pkg::tl_h2d_t mem_tl_win_h2d;
115115
tlul_pkg::tl_d2h_t mem_tl_win_d2h;
116116
rv_dm_reg_pkg::rv_dm_regs_reg2hw_t regs_reg2hw;
117-
logic regs_intg_error, rom_intg_error, dmi_intg_error;
117+
logic regs_intg_error, rom_intg_error, dmi_intg_error, dbg_intg_error;
118118
logic sba_gate_intg_error, rom_gate_intg_error, dmi_gate_intg_error;
119119

120120
rv_dm_regs_reg_top u_reg_regs (
@@ -135,7 +135,7 @@ module rv_dm
135135
// Alerts
136136
logic [NumAlerts-1:0] alert_test, alerts;
137137

138-
assign alerts[0] = regs_intg_error | rom_intg_error | dmi_intg_error |
138+
assign alerts[0] = regs_intg_error | rom_intg_error | dmi_intg_error | dbg_intg_error |
139139
sba_gate_intg_error | rom_gate_intg_error | dmi_gate_intg_error;
140140

141141
assign alert_test = {
@@ -436,6 +436,19 @@ module rv_dm
436436
// If DMIDirectTAP is defined, a bound-in DPI module replaces the TAP that's defined
437437
// within the ifndef block
438438
`ifndef DMIDirectTAP
439+
tlul_pkg::tl_h2d_t dbg_tl_h2d_win;
440+
tlul_pkg::tl_d2h_t dbg_tl_d2h_win;
441+
442+
rv_dm_dbg_reg_top u_rv_dm_dbg_reg_top (
443+
.clk_i,
444+
.rst_ni,
445+
.tl_i (dbg_tl_d_i),
446+
.tl_o (dbg_tl_d_o),
447+
.tl_win_o (dbg_tl_h2d_win),
448+
.tl_win_i (dbg_tl_d2h_win),
449+
.intg_err_o(dbg_intg_error)
450+
);
451+
439452
rv_dm_dmi_gate #(
440453
.SecVolatileRawUnlockEn(SecVolatileRawUnlockEn)
441454
) u_rv_dm_dmi_gate (
@@ -446,14 +459,14 @@ module rv_dm
446459
.lc_hw_debug_en_i,
447460
.lc_check_byp_en_i,
448461
.lc_escalate_en_i,
449-
.dbg_tl_h2d_win_i ( dmi_tl_h2d_i ),
450-
.dbg_tl_d2h_win_o ( dmi_tl_d2h_o ),
451-
.dmi_req_valid_o ( dmi_req_valid ),
452-
.dmi_req_ready_i ( dmi_req_ready ),
453-
.dmi_req_o ( dmi_req ),
454-
.dmi_rsp_valid_i ( dmi_rsp_valid ),
455-
.dmi_rsp_ready_o ( dmi_rsp_ready ),
456-
.dmi_rsp_i ( dmi_rsp ),
462+
.dbg_tl_h2d_win_i ( dbg_tl_h2d_win ),
463+
.dbg_tl_d2h_win_o ( dbg_tl_d2h_win ),
464+
.dmi_req_valid_o ( dmi_req_valid ),
465+
.dmi_req_ready_i ( dmi_req_ready ),
466+
.dmi_req_o ( dmi_req ),
467+
.dmi_rsp_valid_i ( dmi_rsp_valid ),
468+
.dmi_rsp_ready_o ( dmi_rsp_ready ),
469+
.dmi_rsp_i ( dmi_rsp ),
457470

458471
// Integrity error
459472
.intg_error_o( dmi_intg_error)
@@ -559,11 +572,12 @@ module rv_dm
559572
`endif
560573
// Tied-off and ignore signals from the DMI interface
561574
assign dmi_intg_error = 1'b0;
575+
assign dbg_intg_error = 1'b0;
562576
assign dmi_gate_intg_error = 1'b0;
563-
assign dmi_tl_d2h_o = tlul_pkg::TL_D2H_DEFAULT;
577+
assign dbg_tl_d_o = tlul_pkg::TL_D2H_DEFAULT;
564578

565579
logic unused_signals;
566-
assign unused_signals = ^{dmi_tl_h2d_i,
580+
assign unused_signals = ^{dbg_tl_d_i,
567581
lc_check_byp_en_i,
568582
lc_escalate_en_i,
569583
strap_en_i,
@@ -686,8 +700,8 @@ module rv_dm
686700
`ASSERT_KNOWN(TlSbaAValidKnown_A, sba_tl_h_o.a_valid)
687701
`ASSERT_KNOWN(TlSbaDReadyKnown_A, sba_tl_h_o.d_ready)
688702

689-
`ASSERT_KNOWN(TlDmiDValidKnown_A, dmi_tl_d2h_o.d_valid)
690-
`ASSERT_KNOWN(TlDmiAReadyKnown_A, dmi_tl_d2h_o.a_ready)
703+
`ASSERT_KNOWN(TlDmiDValidKnown_A, dbg_tl_d_o.d_valid)
704+
`ASSERT_KNOWN(TlDmiAReadyKnown_A, dbg_tl_d_o.a_ready)
691705

692706
`ASSERT_KNOWN(NdmresetOKnown_A, ndmreset_req_o)
693707
`ASSERT_KNOWN(DmactiveOKnown_A, dmactive_o)

‎hw/ip/rv_dm/rtl/rv_dm_dbg_reg_top.sv‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
// Copyright lowRISC contributors (OpenTitan project).
2+
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3+
// SPDX-License-Identifier: Apache-2.0
4+
//
5+
// Register Top module auto-generated by `reggen`
6+
7+
`include "prim_assert.sv"
8+
9+
module rv_dm_dbg_reg_top (
10+
input clk_i,
11+
input rst_ni,
12+
input tlul_pkg::tl_h2d_t tl_i,
13+
output tlul_pkg::tl_d2h_t tl_o,
14+
15+
// Output port for window
16+
output tlul_pkg::tl_h2d_t tl_win_o,
17+
input tlul_pkg::tl_d2h_t tl_win_i,
18+
19+
// To HW
20+
21+
// Integrity check errors
22+
output logic intg_err_o
23+
);
24+
25+
import rv_dm_reg_pkg::* ;
26+
27+
28+
// Add an unloaded flop to make use of clock / reset
29+
// This is done to specifically address lint complaints of unused clocks/resets
30+
// Since the flop is unloaded it will be removed during synthesis
31+
logic unused_reg;
32+
always_ff @(posedge clk_i or negedge rst_ni) begin
33+
if (!rst_ni) begin
34+
unused_reg <= '0;
35+
end else begin
36+
unused_reg <= tl_i.a_valid;
37+
end
38+
end
39+
40+
41+
42+
// Since there are no registers in this block, commands are routed through to windows which
43+
// can report their own integrity errors.
44+
assign intg_err_o = 1'b0;
45+
46+
// outgoing integrity generation
47+
tlul_pkg::tl_d2h_t tl_o_pre;
48+
tlul_rsp_intg_gen #(
49+
.EnableRspIntgGen(1),
50+
.EnableDataIntgGen(0)
51+
) u_rsp_intg_gen (
52+
.tl_i(tl_o_pre),
53+
.tl_o(tl_o)
54+
);
55+
56+
assign tl_win_o = tl_i;
57+
assign tl_o_pre = tl_win_i;
58+
59+
// Unused signal tieoff
60+
endmodule

‎hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ package rv_dm_reg_pkg;
1313
// Address widths within the block
1414
parameter int RegsAw = 4;
1515
parameter int MemAw = 12;
16+
parameter int DbgAw = 9;
1617

1718
///////////////////////////////////////////////
1819
// Typedefs for registers for regs interface //
@@ -983,4 +984,9 @@ package rv_dm_reg_pkg;
983984
4'b 1111 // index[280] RV_DM_FLAGS_255
984985
};
985986

987+
// Window parameters for dbg interface
988+
parameter logic [DbgAw-1:0] RV_DM_DBG_OFFSET = 9'h 0;
989+
parameter int unsigned RV_DM_DBG_SIZE = 'h 200;
990+
parameter int unsigned RV_DM_DBG_IDX = 0;
991+
986992
endpackage

‎hw/ip/rv_dm/rv_dm.core‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ filesets:
2121
files:
2222
- rtl/rv_dm_reg_pkg.sv
2323
- rtl/rv_dm_regs_reg_top.sv
24+
- rtl/rv_dm_dbg_reg_top.sv
2425
- rtl/rv_dm_dmi_gate.sv
2526
- rtl/rv_dm_pkg.sv
2627
- rtl/rv_dm.sv

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