[dv,top_earlgrey] Add vseq stimulus for simulation of the ft personalization manufacturing stage #28494
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This matches the OTP creator partition state after the initial phase of personalization where the new scrambling seeds are deployed and the system is bootstrapped for a second time to load the multi-slot image rescrambled with the new seeds. Signed-off-by: Harry Callahan <[email protected]>
This is unnecessary, as the existing macros already control the sideband pins and this confuses the HOST side since the DEVICE ends up indicating a read is ready before any data has been put into the spi_device buffer. This can be problematic in DV where the testbench can begin a write operation to fetch this new data with the absolute minimum latency. Signed-off-by: Harry Callahan <[email protected]>
This will be used in an future simulation where the wired OTTF channels need to be simulated. Signed-off-by: Harry Callahan <[email protected]>
This allows tests and particularly test-authors to make use of both frontdoor and backdoor -loaded flash images Signed-off-by: Harry Callahan <[email protected]>
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rswarbrick
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| // Monitor the CONSOLE UART throught the test for informational purposes | ||
| fork print_uart_console_items(ROM_CONSOLE_UART); join_none |
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It's not a problem, but is there a reason this isn't in the fork in the body task? Is there something that might appear before we get there?
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No particularly strong reason, I generally prefer, mostly for comprehension, to bring the scheduling constructs up as high as possible.It also gives the option for the caller to enact a finer-grained process control if desired.
This did not work on all simulators, easier to just remove it entirely. Signed-off-by: Harry Callahan <[email protected]>
This will allow child sequences to make use of the object to intect with the DUT over the ottf spi_console. Signed-off-by: Harry Callahan <[email protected]>
The following commit adds a new vseq for this test. This is a seperate commit to aid readers of the diff. Signed-off-by: Harry Callahan <[email protected]>
…ng personalization Note. this test is slow, typically 14hrs on a fast machine without any waveform dumping or debug database access enabled. Signed-off-by: Harry Callahan <[email protected]>
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Typical runtime without debug access / wave dumping of ~14hrs.
Currently uses 'emulation' sku binaries/images, built for the 'silicon_creator' exec env. Also currently uses the test_rom as sigverify currently fails when using the mask_rom and I could not easily track down why. Switching this to use the mask rom is left as a future task.
TODO: Flesh out description here about pre-generation of spi_console payloads, and how to use the memory dumping/reloading to speed up debug. But the code has lots of comments!