Description
Some notes written by Greg:
Worth noting the current controller plus the tile link bus does some very stupid things in particular around ifetch. There's no burst support so when the icache fetches it'll issue a bunch of 32 bit requests. The hyperram controller will process these separately which takes something like 10-12 system clock cycles each. Where say a proper burst transaction might take say 18 cycles to fetch everything for 8 32 bit instructions the current system would take 80 or more. So icache misses are very costly.
Adding proper bursts transactions is complex (requires work on the icache and tile link components), adding a read streaming buffer would be simpler. Here the hyperram controller would speculatively do a larger burst transaction and cache results in an internal buffer. Follow up reads would hit in that buffer rather than start a new hyperram read. The controller can know what came from ifetch (via tilelink IDs) so say always read stream on ifetch and have a heuristic to start it on dside access (or just only read stream on iside). If done well this can provide the same performance as proper burst support just at the cost of more requests coming on the bus.