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Enable 8-bit and 16-bit memory accesses via the SBA interface to the debug module

Status: Open.

#429 In lowRISC/sonata-system;

· resistor opened on Jun 25, 2025

Wavejson broken in documentation

Status: Open.

#423 In lowRISC/sonata-system;

· marnovandermaas opened on Jun 10, 2025

JTAG DPI tested in CI

Status: Open.

#415 In lowRISC/sonata-system;

· marnovandermaas opened on May 15, 2025

HyperRAM burst support

enhancementNew feature or requestNew feature or request

Status: Open.

#393 In lowRISC/sonata-system;

· marnovandermaas opened on Mar 26, 2025

Unique board ID

enhancementNew feature or requestNew feature or request

Status: Open.

#392 In lowRISC/sonata-system;

· marnovandermaas opened on Mar 25, 2025

Hardware acceleration for CHERIoT revocation sweeps

enhancementNew feature or requestNew feature or request

Status: Open.

#386 In lowRISC/sonata-system;

· marnovandermaas opened on Feb 21, 2025

IP to suspend/reset on both FPGA and sim

enhancementNew feature or requestNew feature or request

Status: Open.

#380 In lowRISC/sonata-system;

· marnovandermaas opened on Jan 17, 2025

Rename <code>xbar_main.json</code> to <code>xbar_main.json.tpl</code>. Then rename <code>xbar_main_generated.hjson</code> to <code>xbar_main.json</code>.

Status: Open.

#348 In lowRISC/sonata-system;

· marnovandermaas opened on Nov 12, 2024

[CI] Enable cherirtos testsuite on the FPGA Job

Status: Open.

#250 In lowRISC/sonata-system;

· engdoreis opened on Oct 16, 2024

CHERI sanity test has an illegal instruction

Status: Open.

#206 In lowRISC/sonata-system;

· marnovandermaas opened on Sep 25, 2024

Wavedrom rendering broken in sonata documentation

Status: Open.

#199 In lowRISC/sonata-system;

· GregAC opened on Sep 20, 2024

SECDED errors from the SRAM can not be signalled for ReadModifyWrite operations.

Status: Open.

#179 In lowRISC/sonata-system;

· ColinDBates opened on Sep 3, 2024