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* Technology mapper * Tech mapper fixes * Tech mapper test updates * Updates and fixes * Mapper updates: switching power optimization and templates restructuring * Mapper: added option to exploit logic sharing, name modifications, tests and experiments updates * minor fixes * Modified test: from exact_map to map * Added P-enumeration and N-matching option in library and mapping to support bigger cell libraries, improved mapping performances, fixed error when truth table minimization is false, increased the cut limit to 50, updated tests for changes * Added inverter usage in exact mapping * removed always_inline to avoid compiler error on Windows * Added mapper documentation * docs fix * Add binding view for mapped networks, added i/o code to write mapped networks in verilog * Added buffering in mapping * Simplified write_verilog for mapped networks, added and updated tests, minor fixes * Added compatibility with multiple pins in Genlib libraries, changed experiment setup for MIG map reading AIGs into MIGs * Support pin names from genlib, better checks on pins parsing * Genilb test corrections * Supergates importing and representation utilities * Updates for supergates support * Added supergates support * Moved gates usage report to binding_view * Test fixes for new library structure * Added report commands in binding_view * Added new tests for supergates, modified supergates insertion procedure to avoid duplicated gates * Added NP-configurations of supergates, use of phmap for better performances, added tests for mapping with supergates * Added tests for binding_library * Fixes * Fixes cast * Added tests to improve coverage * Header and description fixes * Fixes in constant gates for write_verilog, extended usage of topo_view in mapping * Added new mapper, library, supergates, and i/o documentation * Updates to the documentation * Minor fixes and error reporting in mapper * Small fix * bux fix in AQFP network * fix in binding view * Removed random truth table in akers_synthesis test cases, AQFP network fix
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