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@asicsforthemasses

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  1. basic-ecp5-pcb basic-ecp5-pcb Public

    Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

    Verilog 98 23

  2. vga-clock vga-clock Public

    Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

    Verilog 58 11

  3. teensy-audio-fx teensy-audio-fx Public

    Playable effects modeled on the Teenage Engineering Pocket operator series. Featuring Teensy 4 for audio processing.

    C++ 73 6

  4. caravel_user_project caravel_user_project Public

    Forked from efabless/caravel_user_project

    Zero to ASIC group submission for MPW2

    Verilog 13 3

  5. logLUTs logLUTs Public

    Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.

    Python 20 3

  6. multi_project_tools multi_project_tools Public

    tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

    Python 35 14