flag to run simulation in reverse

include/algorithms/simulation/simple_simulation.hpp

@@ -13,9 +13,9 @@
 #include "core/circuit.hpp"
 #include "core/properties.hpp"
 
 #include <boost/dynamic_bitset.hpp>
 #include <functional>
 #include <memory>
 
 namespace syrec {
 
@@ -30,7 +30,7 @@
     * @param g     The gate to be simulated
     * @param input An input pattern
     */
     void coreGateSimulation(const Gate& g, boost::dynamic_bitset<>& input);
 
     /**
     * @brief Simple Simulation function for a circuit
@@ -60,6 +60,6 @@
     * </table>
     */
     void simpleSimulation(boost::dynamic_bitset<>& output, const Circuit& circ, const boost::dynamic_bitset<>& input,
-                          const Properties::ptr& statistics = Properties::ptr());
+                          const Properties::ptr& statistics = Properties::ptr(), const bool reverse = false);
 
 } // namespace syrec

src/algorithms/simulation/simple_simulation.cpp

@@ -18,6 +18,7 @@
 #include <boost/dynamic_bitset/dynamic_bitset.hpp>
 #include <cstddef>
 #include <iostream>
+#include <ranges>
 
 namespace syrec {
 
@@ -58,7 +59,7 @@
     }
 
     void simpleSimulation(boost::dynamic_bitset<>& output, const Circuit& circ, const boost::dynamic_bitset<>& input,
-                          const Properties::ptr& statistics) {
+                          const Properties::ptr& statistics, const bool reverse) {
         Timer<PropertiesTimer> t;
 
         if (statistics) {
@@ -67,8 +68,14 @@
         }
 
         output = input;
-        for (const auto& g: circ) {
-            coreGateSimulation(*g, output);
+        if (reverse) {
+            for (const auto& g: std::ranges::reverse_view(circ)) {
+                coreGateSimulation(*g, output);
+            }
+        } else {
+            for (const auto& g: circ) {
+                coreGateSimulation(*g, output);
+            }
         }
 
         if (statistics) {

src/python/bindings.cpp

@@ -100,5 +100,5 @@ PYBIND11_MODULE(pysyrec, m) {
 
     m.def("cost_aware_synthesis", &CostAwareSynthesis::synthesize, "circ"_a, "program"_a, "settings"_a = Properties::ptr(), "statistics"_a = Properties::ptr(), "Cost-aware synthesis of the SyReC program.");
     m.def("line_aware_synthesis", &LineAwareSynthesis::synthesize, "circ"_a, "program"_a, "settings"_a = Properties::ptr(), "statistics"_a = Properties::ptr(), "Line-aware synthesis of the SyReC program.");
-    m.def("simple_simulation", &simpleSimulation, "output"_a, "circ"_a, "input"_a, "statistics"_a = Properties::ptr(), "Simulation of the synthesized circuit circ.");
+    m.def("simple_simulation", &simpleSimulation, "output"_a, "circ"_a, "input"_a, "statistics"_a = Properties::ptr(), "reverse"_a = false, "Simulation of the synthesized circuit circ.");
 }

test/python/test_syrec.py

@@ -92,6 +92,7 @@ def test_simulation_no_lines(data_line_aware_simulation: dict[str, Any]) -> None
 
         my_inp_bitset = syrec.bitset(circ.lines)
         my_out_bitset = syrec.bitset(circ.lines)
+        my_out_bitset2 = syrec.bitset(circ.lines)
         set_list = data_line_aware_simulation[file_name]["set_lines"]
 
         for set_index in set_list:
@@ -100,6 +101,10 @@ def test_simulation_no_lines(data_line_aware_simulation: dict[str, Any]) -> None
         syrec.simple_simulation(my_out_bitset, circ, my_inp_bitset)
         assert data_line_aware_simulation[file_name]["sim_out"] == str(my_out_bitset)
 
+        # Check reversed simulation
+        syrec.simple_simulation(my_out_bitset2, circ, my_out_bitset, reverse=True)
+        assert str(my_out_bitset2) == str(my_inp_bitset)
+
 
 def test_simulation_add_lines(data_cost_aware_simulation: dict[str, Any]) -> None:
     for file_name in data_cost_aware_simulation:
@@ -112,6 +117,7 @@ def test_simulation_add_lines(data_cost_aware_simulation: dict[str, Any]) -> Non
 
         my_inp_bitset = syrec.bitset(circ.lines)
         my_out_bitset = syrec.bitset(circ.lines)
+        my_out_bitset2 = syrec.bitset(circ.lines)
         set_list = data_cost_aware_simulation[file_name]["set_lines"]
 
         for set_index in set_list:
@@ -120,6 +126,10 @@ def test_simulation_add_lines(data_cost_aware_simulation: dict[str, Any]) -> Non
         syrec.simple_simulation(my_out_bitset, circ, my_inp_bitset)
         assert data_cost_aware_simulation[file_name]["sim_out"] == str(my_out_bitset)
 
+        # Check reversed simulation
+        syrec.simple_simulation(my_out_bitset2, circ, my_out_bitset, reverse=True)
+        assert str(my_out_bitset2) == str(my_inp_bitset)
+
 
 def test_no_lines_to_qasm(data_line_aware_synthesis: dict[str, Any]) -> None:
     for file_name in data_line_aware_synthesis:

test/unittests/test_cost_aware_simulation.cpp

@@ -16,12 +16,12 @@
 
 #include "gtest/gtest.h"
 #include <algorithm>
 #include <boost/dynamic_bitset.hpp>
 #include <nlohmann/json.hpp>
 #include <string>
 #include <vector>
 
 using json = nlohmann::json;
 
 using namespace syrec;
 
@@ -30,10 +30,10 @@
     std::string             testConfigsDir  = "./configs/";
     std::string             testCircuitsDir = "./circuits/";
     std::string             fileName;
     boost::dynamic_bitset<> input;
-    boost::dynamic_bitset<> output;
+    boost::dynamic_bitset<> output, output2;
     std::vector<int>        setLines;
-    std::string             expectedSimOut;
+    std::string             expectedSimOut, expectedSimIn;
     std::string             outputString;
 
     void SetUp() override {
@@ -78,11 +78,18 @@
     }
 
     output.resize(circ.getLines());
+    output2.resize(circ.getLines());
 
     simpleSimulation(output, circ, input, statistics);
 
     boost::to_string(output, outputString);
     std::reverse(outputString.begin(), outputString.end());
 
     EXPECT_EQ(expectedSimOut, outputString);
+
+    // Check reversed simulation
+    simpleSimulation(output2, circ, output, statistics, true);
+    boost::to_string(output2, outputString);
+    boost::to_string(input, expectedSimIn);
+    EXPECT_EQ(expectedSimIn, outputString);
 }

test/unittests/test_line_aware_simulation.cpp

@@ -31,9 +31,9 @@ class SyrecSimulationTest: public testing::TestWithParam<std::string> {
     std::string             testCircuitsDir = "./circuits/";
     std::string             fileName;
     boost::dynamic_bitset<> input;
-    boost::dynamic_bitset<> output;
+    boost::dynamic_bitset<> output, output2;
     std::vector<int>        setLines;
-    std::string             expectedSimOut;
+    std::string             expectedSimOut, expectedSimIn;
     std::string             outputString;
 
     void SetUp() override {
@@ -78,11 +78,18 @@ TEST_P(SyrecSimulationTest, GenericSimulationTest) {
     }
 
     output.resize(circ.getLines());
+    output2.resize(circ.getLines());
 
     simpleSimulation(output, circ, input, statistics);
 
     boost::to_string(output, outputString);
     std::reverse(outputString.begin(), outputString.end());
 
     EXPECT_EQ(expectedSimOut, outputString);
+
+    // Check reversed simulation
+    simpleSimulation(output2, circ, output, statistics, true);
+    boost::to_string(output2, outputString);
+    boost::to_string(input, expectedSimIn);
+    EXPECT_EQ(expectedSimIn, outputString);
 }