improve timing constraints with multicycle paths

nand2mario · Nov 16, 2024 · f885090 · f885090
1 parent 6323586
commit f885090
Show file tree

Hide file tree

Showing 9 changed files with 43 additions and 29 deletions.
diff --git a/build.tcl b/build.tcl
@@ -20,6 +20,7 @@ if {$dev eq "nano20k"} {
     add_file -type cst "src/nano20k/nestang.cst"
     add_file -type verilog "src/nano20k/gowin_pll_hdmi.v"
     add_file -type verilog "src/nano20k/gowin_pll_nes.v"
+    add_file -type sdc "src/nano20k/nestang.sdc"
     # nano20k supports both controllers simultaneously
     set_option -output_base_name nestang_${dev}
 } elseif {$dev eq "primer25k"} {
@@ -36,9 +37,10 @@ if {$dev eq "nano20k"} {
     add_file -type verilog "src/primer25k/gowin_pll_27.v"
     add_file -type verilog "src/primer25k/gowin_pll_hdmi.v"
     add_file -type verilog "src/primer25k/gowin_pll_nes.v"
+    add_file -type sdc "src/primer25k/nestang.sdc"
     set_option -output_base_name nestang_${dev}_${controller}
 } elseif {$dev eq "mega60k"} {
-    set_device GW5AT-LV60PG484AC1/10 -device_version B
+    set_device GW5AT-LV60PG484AC1/I0 -device_version B
     if {$controller eq "snes"} {
         add_file src/mega60k/config_snescontroller.v
         add_file -type cst "src/mega60k/nestang_snescontroller.cst"
@@ -52,6 +54,7 @@ if {$dev eq "nano20k"} {
     add_file -type verilog "src/primer25k/gowin_pll_27.v"
     add_file -type verilog "src/primer25k/gowin_pll_hdmi.v"
     add_file -type verilog "src/primer25k/gowin_pll_nes.v"
+    add_file -type sdc "src/primer25k/nestang.sdc"
     set_option -output_base_name nestang_${dev}_${controller}
 } else {
     error "Unknown device $dev"
@@ -114,6 +117,7 @@ set_option -synthesis_tool gowinsynthesis
 set_option -top_module nestang_top
 set_option -verilog_std sysv2017
 set_option -rw_check_on_ram 1
+# set_option -place_option 2
 set_option -use_mspi_as_gpio 1
 set_option -use_ready_as_gpio 1
 set_option -use_done_as_gpio 1

diff --git a/buildall.bat b/buildall.bat
@@ -1,6 +1,7 @@
 
 @echo off
 set GWSH=..\..\Gowin_V1.9.9_x64\IDE\bin\gw_sh
+set GWSH_NEW=..\..\Gowin_V1.9.10.03_x64\IDE\bin\gw_sh
 
 echo. 
 echo ============ Building nano20k ===============
@@ -17,6 +18,11 @@ echo ============ Building primer25k with ds2 controller ===============
 echo.
 %GWSH% build.tcl primer25k ds2
 
+echo.
+echo ============ Building mega60k with ds2 controller ===============
+echo.
+%GWSH_NEW% build.tcl mega60k ds2
+
 dir impl\pnr\*.fs
 
 echo "All done."

diff --git a/impl/nestang_mega60k_process_config.json b/impl/nestang_mega60k_process_config.json
@@ -57,7 +57,7 @@
  "PlaceInRegToIob" : true,
  "PlaceIoRegToIob" : true,
  "PlaceOutRegToIob" : true,
- "Place_Option" : "2",
+ "Place_Option" : "0",
  "Process_Configuration_Verion" : "1.0",
  "Promote_Physical_Constraint_Warning_to_Error" : true,
  "READY" : false,

diff --git a/src/mappers/MMC5.sv b/src/mappers/MMC5.sv
@@ -83,7 +83,7 @@ reg [7:0] multiplier_2;
 wire [15:0] multiply_result = multiplier_1 * multiplier_2;
 
 // nand2mario FIXME: this uses registers instead of BRAM on 1.9.10_03
-reg [7:0] expansion_ram[0:1023]; // Block RAM, otherwise we need to time multiplex..
+reg [7:0] expansion_ram[0:1023] /* synthesis syn_ramstyle="block_ram" */ ; // Block RAM, otherwise we need to time multiplex..
 reg [7:0] last_read_ram;
 reg [7:0] last_read_exattr;
 reg [7:0] last_read_vram;

diff --git a/src/nano20k/nestang.cst b/src/nano20k/nestang.cst
@@ -9,8 +9,8 @@
 
 IO_LOC "sys_clk" 4;
 IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
-IO_LOC "reset2" 48;
-IO_PORT "reset2" PULL_MODE=DOWN BANK_VCCIO=3.3;
+// IO_LOC "reset2" 48;
+// IO_PORT "reset2" PULL_MODE=DOWN BANK_VCCIO=3.3;
 IO_LOC "s1" 88;
 IO_PORT "s1" PULL_MODE=NONE BANK_VCCIO=3.3;
 

diff --git a/src/nano20k/nestang.sdc b/src/nano20k/nestang.sdc
@@ -1,15 +1,16 @@
 
 // NES clocks
-create_clock -name clk -period 37.04 [get_nets {sys_clk}]       // 27 Mhz
-//create_generated_clock -name clk -source [get_nets {fclk}] -master_clock pclk -divide_by 3 [get_nets {clk}]     // 32.25 Mhz
-
-// USB clock
-//create_clock -name clk_usb -period 83.33 [get_nets {clk_usb}]       // 12 Mhz
+create_clock -name sys_clk -period 37.04 [get_nets {sys_clk}]       // 27 Mhz
+create_clock -name fclk -period 15.43 [get_nets {fclk}]            // 64.8 Mhz
+create_generated_clock -name clk -source [get_nets {fclk}] -divide_by 3 [get_nets {clk}] // 21.6 Mhz
 
 // HDMI clocks
 create_clock -name hclk5 -period 2.6936 [get_nets {hclk5}]                    // 371.25 Mhz
-//create_generated_clock -name clk_p -source [get_nets {clk_p}] -master_clock clk_p5 -divide_by 5 [get_nets {clk_p}]     // 74.25 Mhz: 720p pixel clock
 
-//set_clock_groups -asynchronous -group [get_clocks {pclk} get_clocks{clk}] -group [get_clocks {clk_p5} get_clocks{clk_p}]
-report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
+// NES/iosys to SDRAM, 3 fclk cycles
+set_multicycle_path 3 -end -setup -from [get_clocks {clk}] -to [get_clocks {fclk}]
+set_multicycle_path 2 -end -hold -from [get_clocks {clk}] -to [get_clocks {fclk}]
+
+// SDRAM to NES/iosys, 2 fclk cycles
+set_multicycle_path 2 -start -setup -from [get_clocks {fclk}] -to [get_clocks {clk}]
+set_multicycle_path 1 -start -hold -from [get_clocks {fclk}] -to [get_clocks {clk}]
diff --git a/src/primer25k/nestang.cst b/src/primer25k/nestang.cst
@@ -4,8 +4,8 @@ IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=OFF BANK_VCCIO=3.3;
 IO_LOC "s1" H11;
 IO_PORT "s1" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
 
-IO_LOC "reset2" H10;        // S2
-IO_PORT "reset2" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
+// IO_LOC "reset2" H10;        // S2
+// IO_PORT "reset2" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
 
 // HDMI (USB-A side PMOD)
 //IO_LOC "tmds_clk_p" H5,J5;

diff --git a/src/primer25k/nestang.sdc b/src/primer25k/nestang.sdc
@@ -1,15 +1,18 @@
-
 // NES clocks
-create_clock -name clk -period 20 [get_nets {sys_clk}]       // 50 Mhz
-//create_generated_clock -name clk -source [get_nets {pclk}] -master_clock pclk -divide_by 3 [get_nets {clk}]     // 32.25 Mhz
-
-// USB clock
-//create_clock -name clk_usb -period 83.33 [get_nets {clk_usb}]       // 12 Mhz
+create_clock -name sys_clk -period 20 [get_nets {sys_clk}]       // 50 Mhz
+create_clock -name fclk -period 15.51 [get_nets {fclk}]          // 64.4737 Mhz
+create_generated_clock -name clk -source [get_nets {fclk}] -divide_by 3 [get_nets {clk}] // 21.4912 Mhz
 
 // HDMI clocks
-create_clock -name hclk5 -period 2.6936 [get_nets {hclk5}]                    // 371.25 Mhz
-//create_generated_clock -name clk_p -source [get_nets {clk_p}] -master_clock clk_p5 -divide_by 5 [get_nets {clk_p}]     // 74.25 Mhz: 720p pixel clock
+create_clock -name hclk5 -period 2.6936 [get_nets {hclk5}]       // 371.25 Mhz
+
+// NES/iosys to SDRAM, 3 fclk cycles
+set_multicycle_path 3 -end -setup -from [get_clocks {clk}] -to [get_clocks {fclk}]
+set_multicycle_path 2 -end -hold -from [get_clocks {clk}] -to [get_clocks {fclk}]
+
+// SDRAM to NES/iosys, 2 fclk cycles
+set_multicycle_path 2 -start -setup -from [get_clocks {fclk}] -to [get_clocks {clk}]
+set_multicycle_path 1 -start -hold -from [get_clocks {fclk}] -to [get_clocks {clk}]
 
-//set_clock_groups -asynchronous -group [get_clocks {pclk} get_clocks{clk}] -group [get_clocks {clk_p5} get_clocks{clk_p}]
-report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
+# report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
+# report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
diff --git a/src/primer25k/nestang_snescontroller.cst b/src/primer25k/nestang_snescontroller.cst
@@ -4,8 +4,8 @@ IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=OFF BANK_VCCIO=3.3;
 IO_LOC "s1" H11;
 IO_PORT "s1" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
 
-IO_LOC "reset2" H10;        // S2
-IO_PORT "reset2" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
+// IO_LOC "reset2" H10;        // S2
+// IO_PORT "reset2" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
 
 // HDMI (USB-A side PMOD)
 //IO_LOC "tmds_clk_p" H5,J5;