Reset mechanism doesn't work well when ADC clock frequency is high

[jpcrypt]

Same issue as newaetech/chipwhisperer#559

The source of the problem appears to be that the reset_from_reg-driven whole-FPGA reset (in https://github.com/newaetech/chipwhisperer-husky-fpga/blob/develop/fpga/hdl/reg_openadc.v) is flaky.

Using new_reset instead, by writing the register at address RESET, appears to resolve the issue.