[MC] Use MCRegister and remove implicit casts from MCRegister to unsi…

…gned. NFC

llvm/include/llvm/MC/MCInstrAnalysis.h

@@ -85,8 +85,8 @@ class MCInstrAnalysis {
     if (isBranch(Inst) || isCall(Inst) || isReturn(Inst) ||
         isIndirectBranch(Inst))
       return true;
-    unsigned PC = MCRI.getProgramCounter();
-    if (PC == 0)
+    MCRegister PC = MCRI.getProgramCounter();
+    if (!PC)
       return false;
     return Info->get(Inst.getOpcode()).hasDefOfPhysReg(Inst, PC, MCRI);
   }

llvm/include/llvm/MC/MCInstrDesc.h

@@ -584,13 +584,13 @@ class MCInstrDesc {
 
   /// Return true if this instruction implicitly
   /// uses the specified physical register.
-  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
+  bool hasImplicitUseOfPhysReg(MCRegister Reg) const {
     return is_contained(implicit_uses(), Reg);
   }
 
   /// Return true if this instruction implicitly
   /// defines the specified physical register.
-  bool hasImplicitDefOfPhysReg(unsigned Reg,
+  bool hasImplicitDefOfPhysReg(MCRegister Reg,
                                const MCRegisterInfo *MRI = nullptr) const;
 
   /// Return the scheduling class for this instruction.  The
@@ -617,7 +617,7 @@ class MCInstrDesc {
 
   /// Return true if this instruction defines the specified physical
   /// register, either explicitly or implicitly.
-  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
+  bool hasDefOfPhysReg(const MCInst &MI, MCRegister Reg,
                        const MCRegisterInfo &RI) const;
 };
 

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

@@ -13,6 +13,7 @@
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCRegister.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/SMLoc.h"
 #include "llvm/TargetParser/SubtargetFeature.h"
@@ -24,7 +25,6 @@ namespace llvm {
 class MCContext;
 class MCInst;
 class MCInstrInfo;
-class MCRegister;
 class MCStreamer;
 class MCSubtargetInfo;
 class MCSymbol;
@@ -483,7 +483,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
                                        bool MatchingInlineAsm) = 0;
 
   /// Allows targets to let registers opt out of clobber lists.
-  virtual bool omitRegisterFromClobberLists(unsigned RegNo) { return false; }
+  virtual bool omitRegisterFromClobberLists(MCRegister Reg) { return false; }
 
   /// Allow a target to add special case operand matching for things that
   /// tblgen doesn't/can't handle effectively. For example, literal

llvm/include/llvm/MC/MCRegisterInfo.h

@@ -71,7 +71,7 @@ class MCRegisterClass {
   /// contains - Return true if the specified register is included in this
   /// register class.  This does not include virtual registers.
   bool contains(MCRegister Reg) const {
-    unsigned RegNo = unsigned(Reg);
+    unsigned RegNo = Reg.id();
     unsigned InByte = RegNo % 8;
     unsigned Byte = RegNo / 8;
     if (Byte >= RegSetSize)
@@ -188,7 +188,7 @@ class MCRegisterInfo {
   DenseMap<MCRegister, int> L2CVRegs;         // LLVM to CV regs mapping
 
   mutable std::vector<std::vector<MCPhysReg>> RegAliasesCache;
-  ArrayRef<MCPhysReg> getCachedAliasesOf(MCPhysReg R) const;
+  ArrayRef<MCPhysReg> getCachedAliasesOf(MCRegister R) const;
 
   /// Iterator class that can traverse the differentially encoded values in
   /// DiffLists. Don't use this class directly, use one of the adaptors below.
@@ -358,16 +358,16 @@ class MCRegisterInfo {
     return PCReg;
   }
 
-  const MCRegisterDesc &operator[](MCRegister RegNo) const {
-    assert(RegNo < NumRegs &&
+  const MCRegisterDesc &operator[](MCRegister Reg) const {
+    assert(Reg.id() < NumRegs &&
            "Attempting to access record for invalid register number!");
-    return Desc[RegNo];
+    return Desc[Reg.id()];
   }
 
   /// Provide a get method, equivalent to [], but more useful with a
   /// pointer to this object.
-  const MCRegisterDesc &get(MCRegister RegNo) const {
-    return operator[](RegNo);
+  const MCRegisterDesc &get(MCRegister Reg) const {
+    return operator[](Reg);
   }
 
   /// Returns the physical register number of sub-register "Index"
@@ -457,11 +457,11 @@ class MCRegisterInfo {
     return RegClassStrings + Class->NameIdx;
   }
 
-   /// Returns the encoding for RegNo
-  uint16_t getEncodingValue(MCRegister RegNo) const {
-    assert(RegNo < NumRegs &&
+   /// Returns the encoding for Reg
+  uint16_t getEncodingValue(MCRegister Reg) const {
+    assert(Reg.id() < NumRegs &&
            "Attempting to get encoding for invalid register number!");
-    return RegEncodingTable[RegNo];
+    return RegEncodingTable[Reg.id()];
   }
 
   /// Returns true if RegB is a sub-register of RegA.

llvm/lib/MC/MCInstrDesc.cpp

@@ -21,23 +21,23 @@ bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
                                        const MCRegisterInfo &RI) const {
   if (isBranch() || isCall() || isReturn() || isIndirectBranch())
     return true;
-  unsigned PC = RI.getProgramCounter();
-  if (PC == 0)
+  MCRegister PC = RI.getProgramCounter();
+  if (!PC)
     return false;
   if (hasDefOfPhysReg(MI, PC, RI))
     return true;
   return false;
 }
 
-bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
+bool MCInstrDesc::hasImplicitDefOfPhysReg(MCRegister Reg,
                                           const MCRegisterInfo *MRI) const {
   for (MCPhysReg ImpDef : implicit_defs())
     if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef)))
       return true;
   return false;
 }
 
-bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
+bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, MCRegister Reg,
                                   const MCRegisterInfo &RI) const {
   for (int i = 0, e = NumDefs; i != e; ++i)
     if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&

llvm/lib/MC/MCParser/AsmParser.cpp

@@ -6009,7 +6009,7 @@ bool AsmParser::parseMSInlineAsm(
   SmallVector<bool, 4> OutputDeclsAddressOf;
   SmallVector<std::string, 4> InputConstraints;
   SmallVector<std::string, 4> OutputConstraints;
-  SmallVector<unsigned, 4> ClobberRegs;
+  SmallVector<MCRegister, 4> ClobberRegs;
 
   SmallVector<AsmRewrite, 4> AsmStrRewrites;
 

llvm/lib/MC/MCParser/MasmParser.cpp

@@ -7349,7 +7349,7 @@ bool MasmParser::parseMSInlineAsm(
   SmallVector<bool, 4> OutputDeclsAddressOf;
   SmallVector<std::string, 4> InputConstraints;
   SmallVector<std::string, 4> OutputConstraints;
-  SmallVector<unsigned, 4> ClobberRegs;
+  SmallVector<MCRegister, 4> ClobberRegs;
 
   SmallVector<AsmRewrite, 4> AsmStrRewrites;
 

llvm/lib/MC/MCRegisterInfo.cpp

@@ -83,8 +83,8 @@ class MCRegAliasIteratorImpl {
 };
 } // namespace
 
-ArrayRef<MCPhysReg> MCRegisterInfo::getCachedAliasesOf(MCPhysReg R) const {
-  auto &Aliases = RegAliasesCache[R];
+ArrayRef<MCPhysReg> MCRegisterInfo::getCachedAliasesOf(MCRegister R) const {
+  auto &Aliases = RegAliasesCache[R.id()];
   if (!Aliases.empty())
     return Aliases;
 
@@ -99,7 +99,7 @@ ArrayRef<MCPhysReg> MCRegisterInfo::getCachedAliasesOf(MCPhysReg R) const {
   // Always put "self" at the end, so the iterator can choose to ignore it.
   // For registers without aliases, it also serves as a sentinel value that
   // tells us to not recompute the alias set.
-  Aliases.push_back(R);
+  Aliases.push_back(R.id());
   Aliases.shrink_to_fit();
   return Aliases;
 }

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

@@ -1215,7 +1215,7 @@ class X86AsmParser : public MCTargetAsmParser {
                                     uint64_t &ErrorInfo,
                                     bool MatchingInlineAsm);
 
-  bool omitRegisterFromClobberLists(unsigned RegNo) override;
+  bool omitRegisterFromClobberLists(MCRegister Reg) override;
 
   /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
   /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
@@ -4659,8 +4659,8 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
                MatchingInlineAsm);
 }
 
-bool X86AsmParser::omitRegisterFromClobberLists(unsigned RegNo) {
-  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
+bool X86AsmParser::omitRegisterFromClobberLists(MCRegister Reg) {
+  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg);
 }
 
 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {