[nrf fromtree] platform: nordic_nrf: nrf7120: switch to uart20

platform/ext/target/nordic_nrf/common/core/target_cfg.h

@@ -59,18 +59,12 @@
 /* Only UART20 and UART30 are supported for TF-M tests, which are the
  * Non-secure applications build via the TF-M build system
  */
-#if defined(NRF54L_SERIES)
+#if defined(NRF54L_SERIES) || defined(NRF71_SERIES)
 #if NRF_SECURE_UART_INSTANCE == 20
 #define NS_DRIVER_STDIO     Driver_USART30
 #else
 #define NS_DRIVER_STDIO     Driver_USART20
 #endif
-#elif defined(NRF71_SERIES)
-#if defined(NRF_SECURE_UART_INSTANCE) && (NRF_SECURE_UART_INSTANCE == 00)
-#define NS_DRIVER_STDIO     Driver_USART30
-#else
-#define NS_DRIVER_STDIO     Driver_USART00
-#endif
 #else
 #define NS_DRIVER_STDIO     Driver_USART0
 #endif /* NRF54L_SERIES or NRF71_SERIES */

platform/ext/target/nordic_nrf/common/nrf7120/CMakeLists.txt

@@ -18,6 +18,13 @@ target_include_directories(platform_s
         .
 )
 
+if(NOT NRF_DIR)
+target_include_directories(platform_s
+    PUBLIC
+        memory_service_ranges
+)
+endif()
+
 target_sources(platform_s
     PRIVATE
         ${HAL_NORDIC_PATH}/nrfx/bsp/stable/mdk/system_nrf7120_enga.c

platform/ext/target/nordic_nrf/common/nrf7120/config.cmake

@@ -8,7 +8,7 @@
 
 include(${PLATFORM_PATH}/common/core/config.cmake)
 
-set(SECURE_UART30                       ON         CACHE BOOL      "Enable secure UART" FORCE)
+set(SECURE_UART30                       ON         CACHE BOOL      "Enable secure UART")
 set(BL2                                 OFF        CACHE BOOL      "Whether to build BL2" FORCE)
 set(NRF_NS_SECONDARY                    OFF        CACHE BOOL      "Enable non-secure secondary partition" FORCE)
-set(NRF_SECURE_UART_INSTANCE            30         CACHE STRING    "The UART instance number to use for secure UART" FORCE)
+set(NRF_SECURE_UART_INSTANCE            30         CACHE STRING    "The UART instance number to use for secure UART")

platform/ext/target/nordic_nrf/common/nrf7120/memory_service_ranges/tfm_platform_user_memory_ranges.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__
+#define TFM_PLATFORM_USER_MEMORY_RANGES_H__
+
+#include <tfm_ioctl_core_api.h>
+
+#include <nrfx.h>
+
+
+static const struct tfm_read_service_range ranges[] = {
+	{ .start = 0xFFFFFFFF, .size = 0x0},
+};
+
+static const struct tfm_write32_service_address tfm_write32_service_addresses[] = {
+	/* This is a dummy value because this table cannot be empty */
+	{.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0},
+};
+
+#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */

platform/ext/target/nordic_nrf/common/nrf7120/nrf71_init.c

@@ -6,7 +6,6 @@
  */
 #include <stdint.h>
 #include <nrfx.h>
-#include <nrf_erratas.h>
 
 #ifndef BIT_MASK
 /* Use Zephyr BIT_MASK for unasigned integers */

platform/ext/target/nordic_nrf/common/nrf7120/partition/flash_layout.h

@@ -42,21 +42,17 @@
 /* Use Flash memory to store Code data */
 #define FLASH_BASE_ADDRESS                  (0x0)
 
-/* nRF7120 has 4088 kB of non volatile memory (MRAM) but the last 116kB are reserved
+/* nRF7120 has 4084 kB of non volatile memory (MRAM) but the last 116kB are reserved
  * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along
  * with TF-M later FLPR non volatile memory is not used by TF-M. */
-#define FLASH_TOTAL_SIZE                    (0x3E1000)         /* 3972 kB since the last 116kB are reserved for FLPR */
+#define FLASH_TOTAL_SIZE                    (0x3E0000)         /* 3968 kB since the last 116kB are reserved for FLPR */
 #define TOTAL_ROM_SIZE                       FLASH_TOTAL_SIZE
 
-/* nRF7120 has 1024 kB of volatile memory (SRAM) but only 512kB are reserved for Arm Cortex-M33.
- * RAM_00: 512 Kb - Arm® Cortex®-M33 code and data
- * RAM_01: 256 Kb - ML accelerator
- * RAM_02: 128 Kb - Network Buffer WiFi/Radio system
- * RAM_03: 120 Kb - FLPR code, data and top 8Kb reserved
+/* nRF7120 has 1024 kB of volatile memory (SRAM) but only 768kB are reserved for Arm Cortex-M33.
  * For simplicity and for possible support for running FLPR along
  * with TF-M later FLPR volatile memory is not used by TF-M. */
 #define SRAM_BASE_ADDRESS                   (0x20000000)
-#define TOTAL_RAM_SIZE                      (0x00080000)       /* 512 kB, since other 512 kB are reserved for others */
+#define TOTAL_RAM_SIZE                      (0x000C0000)       /* 768 kB, since other 256 kB are reserved for FLPR */
 
 #define FLASH_S_PARTITION_SIZE                (0x80000)       /* S partition: 512 kB*/
 #define FLASH_NS_PARTITION_SIZE               (0xD3000)       /* NS partition: 844 kB*/

platform/ext/target/nordic_nrf/nrf7120dk_nrf7120_cpuapp/RTE_Device.h

@@ -17,14 +17,14 @@
 #ifndef __RTE_DEVICE_H
 #define __RTE_DEVICE_H
 
-#define RTE_USART00 1
+#define RTE_USART20 1
 
-#define RTE_USART00_PINS         \
+#define RTE_USART20_PINS         \
 {                                \
-        NRF_PSEL(UART_TX,  2, 2),\
-        NRF_PSEL(UART_RX,  2, 0),\
-        NRF_PSEL(UART_RTS, 2, 5),\
-        NRF_PSEL(UART_CTS, 2, 4),\
+        NRF_PSEL(UART_TX,  1, 4),\
+        NRF_PSEL(UART_RX,  1, 5),\
+        NRF_PSEL(UART_RTS, 1, 6),\
+        NRF_PSEL(UART_CTS, 1, 7),\
 }