passing test

test/Makefile

@@ -5,8 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
-
+PROJECT_SOURCES = project.v decoder.v
 ifneq ($(GATES),yes)
 
 # RTL simulation:
@@ -32,7 +31,7 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
 endif
 
 # Include the testbench sources:
-VERILOG_SOURCES += $(PWD)/tb.v 
+VERILOG_SOURCES += $(PWD)/tb.v
 TOPLEVEL = tb
 
 # MODULE is the basename of the Python test file

test/tb.v

@@ -22,7 +22,7 @@ module tb ();
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
 
-  // Replace tt_um_example with your module name:
+  // module name of user project:
   tt_um_nubcore_default_tape user_project (
 
       // Include power ports for the Gate Level test:

test/test.py

@@ -8,7 +8,7 @@
 @cocotb.test()
 async def test_project(dut):
   dut._log.info("Start")
-  
+
   # Our example module doesn't use clock and reset, but we show how to use them here anyway.
   clock = Clock(dut.clk, 10, units="us")
   cocotb.start_soon(clock.start())
@@ -24,9 +24,9 @@ async def test_project(dut):
 
   # Set the input values, wait one clock cycle, and check the output
   dut._log.info("Test")
-  #dut.ui_in.value = 20
-  #dut.uio_in.value = 30
 
   await ClockCycles(dut.clk, 1)
 
-  #assert dut.uo_out.value == 50
+  # Check 7 segment 'dot' is set to low
+  assert dut.uo_out[7].value == 0
+