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Synthesis Bugs in GENPC: Mismatch in CPU Address when SPR changes

Status: Open.

#162 In openrisc/mor1kx;

· rsar97 opened on Jan 27, 2025

Synthesis Bugs: PC and Executed Insn

Status: Open.

#161 In openrisc/mor1kx;

· rsar97 opened on Jan 27, 2025

Synthesis Bugs in the LSU

Status: Open.

#160 In openrisc/mor1kx;

· rsar97 opened on Jan 5, 2025

Status of FEATURE_FASTCONTEXTS in cappuccino

Status: Open.

#158 In openrisc/mor1kx;

· zeldin opened on Jul 5, 2024

An error occurs when logical synthesis is performed using the Design Compiler

Status: Open.

#155 In openrisc/mor1kx;

· RENEK-bool opened on Oct 31, 2023

Setting dcache cache width to 2 or 3 causes failures

Status: Open.

#153 In openrisc/mor1kx;

· stffrdhrn opened on May 13, 2022

Disabling store buffer breaks LSU

Status: Open.

#152 In openrisc/mor1kx;

· stffrdhrn opened on May 13, 2022

Complete formal proofs for LSU, Dcache and CPU modules

Status: Open.

#151 In openrisc/mor1kx;

· stffrdhrn opened on May 13, 2022

Setting DBUS_WB_TYPE = "B3_READ_BURSTING" causes lockup

Status: Open.

#150 In openrisc/mor1kx;

· jefferybond opened on Apr 11, 2022

Unable to write to the EEAR register from the supervisor mode.

Status: Open.

#141 In openrisc/mor1kx;

· Rahul-Kande opened on Sep 3, 2021

The EPCR register is accessible from user mode

Status: Open.

#140 In openrisc/mor1kx;

· Rahul-Kande opened on Sep 3, 2021

The carry flag implementation is not correct for subtract instructions

Status: Open.

#139 In openrisc/mor1kx;

· Rahul-Kande opened on Sep 3, 2021