chore: remove native extension-specific code

crates/circuits/primitives/cuda/include/primitives/constants.h

@@ -15,13 +15,6 @@ inline constexpr size_t PC_BITS = 30;
 inline constexpr size_t DEFAULT_PC_STEP = 4;
 } // namespace program
 
-namespace native {
-inline constexpr size_t AS_IMMEDIATE = 0;
-inline constexpr size_t AS_NATIVE = 4;
-inline constexpr size_t EXT_DEG = 4;
-inline constexpr size_t BETA = 11;
-} // namespace native
-
 namespace poseidon2 {
 inline constexpr size_t CHUNK = 8;
 } // namespace poseidon2

crates/sdk/src/stdin.rs

@@ -1,7 +1,4 @@
-use std::{
-    collections::{HashMap, VecDeque},
-    sync::Arc,
-};
+use std::collections::VecDeque;
 
 use itertools::Itertools;
 use openvm_circuit::arch::{deferral::DeferralState, Streams};
@@ -14,7 +11,6 @@ use serde::{Deserialize, Serialize};
 #[derive(Clone, Default, Serialize, Deserialize)]
 pub struct StdIn<F = crate::F> {
     pub buffer: VecDeque<Vec<F>>,
-    pub kv_store: HashMap<Vec<u8>, Vec<u8>>,
     pub deferrals: Vec<DeferralState>,
 }
 
@@ -43,9 +39,6 @@ impl<F: Field> StdIn<F> {
     pub fn write_field(&mut self, data: &[F]) {
         self.buffer.push_back(data.to_vec());
     }
-    pub fn add_key_value(&mut self, key: Vec<u8>, value: Vec<u8>) {
-        self.kv_store.insert(key, value);
-    }
 }
 
 impl<F: Field> From<StdIn<F>> for Streams<F> {
@@ -55,7 +48,6 @@ impl<F: Field> From<StdIn<F>> for Streams<F> {
             data.push(input);
         }
         let mut ret = Streams::new(data);
-        ret.kv_store = Arc::new(std_in.kv_store);
         ret.deferrals = std_in.deferrals;
         ret
     }

crates/toolchain/openvm/src/io/mod.rs

@@ -56,16 +56,6 @@ fn hint_store_word(ptr: *mut u32) {
     }
 }
 
-/// Load hints by key and append into the input stream.
-#[allow(unused_variables)]
-#[inline(always)]
-pub fn hint_load_by_key(key: &[u8]) {
-    #[cfg(target_os = "zkvm")]
-    openvm_rv32im_guest::hint_load_by_key(key.as_ptr(), key.len() as u32);
-    #[cfg(not(target_os = "zkvm"))]
-    panic!("hint_load_by_key cannot run on non-zkVM platforms");
-}
-
 /// Read the next `len` bytes from the hint stream into a vector.
 pub(crate) fn read_vec_by_len(len: usize) -> Vec<u8> {
     let num_words = len.div_ceil(4);
@@ -126,16 +116,6 @@ pub fn reveal_u32(x: u32, index: usize) {
     println!("reveal {} at byte location {}", x, index * 4);
 }
 
-/// Store u32 `x` to the native address `native_addr` as 4 field element in byte.
-#[allow(unused_variables)]
-#[inline(always)]
-pub fn store_u32_to_native(native_addr: u32, x: u32) {
-    #[cfg(target_os = "zkvm")]
-    openvm_rv32im_guest::store_to_native!(native_addr, x);
-    #[cfg(not(target_os = "zkvm"))]
-    panic!("store_to_native_u32 cannot run on non-zkVM platforms");
-}
-
 /// A no-alloc writer to print to stdout on host machine for debugging purposes.
 pub struct Writer;
 

crates/vm/src/arch/config.rs

@@ -115,7 +115,7 @@ pub const OPENVM_DEFAULT_INIT_FILE_NAME: &str = "openvm_init.rs";
 /// The minimum block size is 4, but RISC-V `lb` only requires alignment of 1 and `lh` only requires
 /// alignment of 2 because the instructions are implemented by doing an access of block size 4.
 const DEFAULT_U8_BLOCK_SIZE: usize = 4;
-const DEFAULT_NATIVE_BLOCK_SIZE: usize = 1;
+const DEFAULT_FIELD_BLOCK_SIZE: usize = 1;
 
 /// Trait for generating a init.rs file that contains a call to moduli_init!,
 /// complex_init!, sw_init! with the supported moduli and curves.
@@ -195,14 +195,11 @@ impl MemoryConfig {
     pub fn empty_address_space_configs(num_addr_spaces: usize) -> Vec<AddressSpaceHostConfig> {
         // All except address spaces 0..4 default to native 32-bit field.
         // By default only address spaces 1..=4 have non-empty cell counts.
-        let mut addr_spaces = vec![
-            AddressSpaceHostConfig::new(
-                0,
-                DEFAULT_NATIVE_BLOCK_SIZE,
-                MemoryCellType::native32()
-            );
-            num_addr_spaces
-        ];
+        let mut addr_spaces =
+            vec![
+                AddressSpaceHostConfig::new(0, DEFAULT_FIELD_BLOCK_SIZE, MemoryCellType::field32());
+                num_addr_spaces
+            ];
         addr_spaces[RV32_IMM_AS as usize] = AddressSpaceHostConfig::new(0, 1, MemoryCellType::Null);
         addr_spaces[RV32_REGISTER_AS as usize] =
             AddressSpaceHostConfig::new(0, DEFAULT_U8_BLOCK_SIZE, MemoryCellType::U8);
@@ -224,14 +221,6 @@ impl MemoryConfig {
         addr_spaces
     }
 
-    /// Config for aggregation usage with only native address space.
-    pub fn aggregation() -> Self {
-        let mut addr_spaces =
-            Self::empty_address_space_configs((1 << 3) + ADDR_SPACE_OFFSET as usize);
-        addr_spaces[openvm_instructions::DEFERRAL_AS as usize].num_cells = 1 << 29;
-        Self::new(3, addr_spaces, POINTER_MAX_BITS, 29, 17, 8)
-    }
-
     pub fn min_block_size_bits(&self) -> Vec<u8> {
         self.addr_spaces
             .iter()
@@ -433,14 +422,14 @@ pub enum MemoryCellType {
     /// Represented in little-endian format.
     U32,
     /// `size` is the size in bytes of the native field type. This should not exceed 8.
-    Native {
+    F {
         size: u8,
     },
 }
 
 impl MemoryCellType {
-    pub fn native32() -> Self {
-        Self::Native {
+    pub fn field32() -> Self {
+        Self::F {
             size: size_of::<u32>() as u8,
         }
     }
@@ -453,7 +442,7 @@ impl AddressSpaceHostLayout for MemoryCellType {
             Self::U8 => size_of::<u8>(),
             Self::U16 => size_of::<u16>(),
             Self::U32 => size_of::<u32>(),
-            Self::Native { size } => *size as usize,
+            Self::F { size } => *size as usize,
         }
     }
 
@@ -470,7 +459,7 @@ impl AddressSpaceHostLayout for MemoryCellType {
             Self::U8 => F::from_u8(*value.get_unchecked(0)),
             Self::U16 => F::from_u16(core::ptr::read(value.as_ptr() as *const u16)),
             Self::U32 => F::from_u32(core::ptr::read(value.as_ptr() as *const u32)),
-            Self::Native { .. } => core::ptr::read(value.as_ptr() as *const F),
+            Self::F { .. } => core::ptr::read(value.as_ptr() as *const F),
         }
     }
 }

crates/vm/src/arch/testing/cpu.rs

@@ -307,10 +307,6 @@ impl<F: VmField> VmChipTestBuilder<F> {
         Self::persistent(mem_config)
     }
 
-    pub fn default_native() -> Self {
-        Self::volatile(MemoryConfig::aggregation())
-    }
-
     fn range_checker_and_memory(
         mem_config: &MemoryConfig,
         init_block_size: usize,

crates/vm/src/arch/vm.rs

@@ -6,13 +6,7 @@
 //!
 //! [VirtualMachine] will similarly be the struct that has done all the setup so it can
 //! execute+prove an arbitrary program for a fixed config - it will internally still hold VmExecutor
-use std::{
-    any::TypeId,
-    borrow::Borrow,
-    collections::{HashMap, VecDeque},
-    marker::PhantomData,
-    sync::Arc,
-};
+use std::{any::TypeId, borrow::Borrow, collections::VecDeque, marker::PhantomData, sync::Arc};
 
 use getset::{Getters, MutGetters, Setters, WithSetters};
 use itertools::{zip_eq, Itertools};
@@ -105,25 +99,11 @@ pub enum GenerationError {
     },
 }
 
-/// A trait for key-value store for `Streams`.
-pub trait KvStore: Send + Sync {
-    fn get(&self, key: &[u8]) -> Option<&[u8]>;
-}
-
-impl KvStore for HashMap<Vec<u8>, Vec<u8>> {
-    fn get(&self, key: &[u8]) -> Option<&[u8]> {
-        self.get(key).map(|v| v.as_slice())
-    }
-}
-
 #[derive(Clone)]
 pub struct Streams<F> {
     pub input_stream: VecDeque<Vec<F>>,
     pub hint_stream: VecDeque<F>,
     pub hint_space: Vec<Vec<F>>,
-    /// The key-value store for hints. Both key and value are byte arrays. Executors which
-    /// read `kv_store` need to encode the key and decode the value.
-    pub kv_store: Arc<dyn KvStore>,
     /// Stores cached deferred operation inputs and outputs. Each idx corresponds to a
     /// unique function that is constrained outside the VM in its own deferral circuit.
     pub deferrals: Vec<DeferralState>,
@@ -135,7 +115,6 @@ impl<F> Streams<F> {
             input_stream: input_stream.into(),
             hint_stream: VecDeque::default(),
             hint_space: Vec::default(),
-            kv_store: Arc::new(HashMap::new()),
             deferrals: Vec::default(),
         }
     }

crates/vm/src/system/cuda/merkle_tree/mod.rs

@@ -495,7 +495,7 @@ mod tests {
                             );
                         }
                     }
-                    MemoryCellType::Native { .. } => {
+                    MemoryCellType::F { .. } => {
                         for i in 0..space.num_cells {
                             initial_memory.write::<F, 1>(
                                 idx as u32,

crates/vm/src/system/memory/adapter/mod.rs

@@ -383,7 +383,7 @@ impl<F, const N: usize> GenericAccessAdapterChipTrait<F> for AccessAdapterChip<F
         // SAFETY: values will be a slice of the cell type
         unsafe {
             match addr_space_layout {
-                MemoryCellType::Native { .. } => {
+                MemoryCellType::F { .. } => {
                     copy_nonoverlapping(
                         values.as_ptr(),
                         row.values.as_mut_ptr() as *mut u8,

crates/vm/src/system/memory/merkle/tests/mod.rs

@@ -197,12 +197,12 @@ fn random_test(
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
         ],
         height + 3,
@@ -290,12 +290,12 @@ fn expand_test_no_accesses() {
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
         ],
         height + 3,
@@ -339,12 +339,12 @@ fn expand_test_negative() {
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
             AddressSpaceHostConfig {
                 num_cells: CHUNK << height,
                 min_block_size: 1,
-                layout: MemoryCellType::Native { size: 4 },
+                layout: MemoryCellType::F { size: 4 },
             },
         ],
         height + 3,

crates/vm/src/system/poseidon2/mod.rs

@@ -1,6 +1,5 @@
-//! Chip to handle **native kernel** instructions for Poseidon2 `compress` and `permute`.
-//! This chip is put in `intrinsics` for organizational convenience, but
-//! it is used as a system chip for persistent memory and as a native kernel chip for aggregation.
+//! Chip to handle Poseidon2 instructions `compress` and `permute`. It is used as a system chip
+//! for persistent memory.
 //!
 //! Note that neither `compress` nor `permute` on its own
 //! is a cryptographic hash. `permute` is a cryptographic permutation, which can be made