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    • Verilog
      Apache License 2.0
      0000Updated Mar 10, 2025Mar 10, 2025
    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      GNU Lesser General Public License v3.0
      6372000Updated Mar 10, 2025Mar 10, 2025
    • SystemVerilog
      Apache License 2.0
      51810Updated Mar 10, 2025Mar 10, 2025
    • kenning

      Public
      Python
      Apache License 2.0
      46100Updated Mar 9, 2025Mar 9, 2025
    • Python
      Apache License 2.0
      3400Updated Mar 8, 2025Mar 8, 2025
    • zephyr

      Public
      Primary GIT Repository for the Zephyr Project
      C
      Apache License 2.0
      7.1k1011Updated Mar 7, 2025Mar 7, 2025
    • renode

      Public
      Renode - virtual development tool for multinode embedded networks
      RobotFramework
      Other
      3103100Updated Mar 7, 2025Mar 7, 2025
    • JavaScript
      Apache License 2.0
      31401Updated Mar 7, 2025Mar 7, 2025
    • tlib

      Public
      C++
      Other
      331803Updated Mar 7, 2025Mar 7, 2025
    • benchalot

      Public
      Benchmark automation tool
      Python
      Apache License 2.0
      0300Updated Mar 7, 2025Mar 7, 2025
    • Python
      Apache License 2.0
      0300Updated Mar 7, 2025Mar 7, 2025
    • C++
      Apache License 2.0
      12310Updated Mar 7, 2025Mar 7, 2025
    • C
      Apache License 2.0
      1000Updated Mar 7, 2025Mar 7, 2025
    • C
      1810Updated Mar 6, 2025Mar 6, 2025
    • C
      Apache License 2.0
      0000Updated Mar 6, 2025Mar 6, 2025
    • Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
      Starlark
      Apache License 2.0
      48000Updated Mar 6, 2025Mar 6, 2025
    • 0000Updated Mar 6, 2025Mar 6, 2025
    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
      Verilog
      BSD 3-Clause "New" or "Revised" License
      611100Updated Mar 6, 2025Mar 6, 2025
    • coverview

      Public
      Coverview
      Vue
      Apache License 2.0
      1100Updated Mar 6, 2025Mar 6, 2025
    • sv-tests

      Public
      Test suite designed to check compliance with the SystemVerilog standard.
      SystemVerilog
      ISC License
      772015Updated Mar 6, 2025Mar 6, 2025
    • rdfm

      Public
      Python
      Apache License 2.0
      62300Updated Mar 6, 2025Mar 6, 2025
    • Python
      Apache License 2.0
      0000Updated Mar 6, 2025Mar 6, 2025
    • FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
      Jupyter Notebook
      ISC License
      1121010Updated Mar 6, 2025Mar 6, 2025
    • Automatic architecture search and hyperparameter optimization for PyTorch
      Python
      Apache License 2.0
      295000Updated Mar 5, 2025Mar 5, 2025
    • Python
      Apache License 2.0
      1310Updated Mar 5, 2025Mar 5, 2025
    • Apache License 2.0
      1100Updated Mar 5, 2025Mar 5, 2025
    • dts2repl

      Public
      Python
      Apache License 2.0
      62221Updated Mar 5, 2025Mar 5, 2025
    • Python
      Apache License 2.0
      15100102Updated Mar 4, 2025Mar 4, 2025
    • i3c-core

      Public
      SystemVerilog
      Apache License 2.0
      5000Updated Mar 4, 2025Mar 4, 2025
    • HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
      SystemVerilog
      Apache License 2.0
      8000Updated Mar 4, 2025Mar 4, 2025