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    61 repositories

    • cva6

      Public
      The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
      asiccpufpgarisc-vsystemverilog-hdlrv64gcariane
      Assembly
      •
      Other
      •815•2.6k•202•7•Updated Jul 29, 2025Jul 29, 2025

    • tristan-isolde-unified-access-page

      Public
      Unified Access Page for the TRISTAN project
      HTML
      •40•17•2•2•Updated Jul 28, 2025Jul 28, 2025

    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
      SystemVerilog
      •
      Other
      •298•402•27•4•Updated Jul 27, 2025Jul 27, 2025

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •36•13•40•5•Updated Jul 25, 2025Jul 25, 2025

    • cv-hpdcache

      Public
      RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
      SystemVerilog
      •
      Other
      •35•89•4•2•Updated Jul 23, 2025Jul 23, 2025

    • cve2

      Public
      The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
      SystemVerilog
      •
      Apache License 2.0
      •636•47•155•10•Updated Jul 17, 2025Jul 17, 2025

    • core-v-mcu

      Public
      This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
      microcontrollerriscvsystemverilogopenhwgroup
      SystemVerilog
      •
      Other
      •63•182•75•10•Updated Jul 17, 2025Jul 17, 2025

    • cva5

      Public
      The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
      SystemVerilog
      •
      Apache License 2.0
      •27•117•4•0•Updated Jul 11, 2025Jul 11, 2025

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      verificationsystemveriloguvmrisc-v
      Assembly
      •
      Other
      •251•572•128•15•Updated Jul 3, 2025Jul 3, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •82•71•34•5•Updated Jun 26, 2025Jun 26, 2025

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      riscvriscv32imfc
      SystemVerilog
      •
      Other
      •460•1.1k•51•11•Updated May 26, 2025May 26, 2025

    • programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      HTML
      •
      Other
      •98•218•9•10•Updated May 22, 2025May 22, 2025

    • osdforum.org

      Public
      The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.
      webdevhugo
      HTML
      •
      Eclipse Public License 2.0
      •6•1•0•0•Updated Apr 22, 2025Apr 22, 2025

    • openhwgroup.org

      Public
      OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…
      webdevhugo
      HTML
      •
      Eclipse Public License 2.0
      •11•18•5•4•Updated Mar 19, 2025Mar 19, 2025

    • cv32e20-dv

      Public
      Assembly
      •
      Apache License 2.0
      •9•1•0•2•Updated Mar 18, 2025Mar 18, 2025

    • core-v-sw

      Public
      Main Repo for the OpenHW Group Software Task Group
      Eclipse Public License 2.0
      •28•17•6•0•Updated Mar 11, 2025Mar 11, 2025

    • cv-mesh

      Public
      Verilog
      •0•3•0•0•Updated Mar 10, 2025Mar 10, 2025

    • core-v-cores

      Public
      CORE-V Family of RISC-V Cores
      19•283•1•1•Updated Feb 13, 2025Feb 13, 2025

    • cv-hpdcache-verif

      Public
      Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
      SystemVerilog
      •
      Apache License 2.0
      •5•16•0•0•Updated Feb 12, 2025Feb 12, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •137•515•39•12•Updated Feb 12, 2025Feb 12, 2025

    • cv32e40s-dv

      Public
      CV32E40S Design-Verification environment
      Assembly
      •
      Apache License 2.0
      •1•0•1•0•Updated Nov 11, 2024Nov 11, 2024

    • cv32e40x

      Public
      4 stage, in-order, compute RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •52•240•31•5•Updated Nov 6, 2024Nov 6, 2024

    • cv32e40s

      Public
      4 stage, in-order, secure RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •27•147•2•2•Updated Oct 31, 2024Oct 31, 2024

    • corev-qemu

      Public
      Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
      C
      •
      Other
      •6.1k•1•0•2•Updated Aug 16, 2024Aug 16, 2024

    • core-v-polara-apu

      Public
      The OpenPiton Platform
      Assembly
      •246•16•0•2•Updated Aug 14, 2024Aug 14, 2024

    • corev-binutils-gdb

      Public
      C
      •
      GNU General Public License v2.0
      •26•9•4•0•Updated Jul 30, 2024Jul 30, 2024

    • corev-llvm-project

      Public
      Other
      •19•17•4•2•Updated Jul 26, 2024Jul 26, 2024

    • core-v-mcu-uvm

      Public
      CORE-V MCU UVM Environment and Test Bench
      SystemVerilog
      •
      Other
      •8•21•16•0•Updated Jul 19, 2024Jul 19, 2024

    • corev-gcc

      Public
      C++
      •
      GNU General Public License v2.0
      •24•26•8•1•Updated Jul 19, 2024Jul 19, 2024

    • core-v-xif

      Public
      RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
      SystemVerilog
      •
      Other
      •28•72•19•1•Updated May 22, 2024May 22, 2024