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    • Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
      C++
      74182327Updated Jul 17, 2025Jul 17, 2025
    • Machine-readable database of the RISC-V specification, and tools to generate various views
      Ruby
      518215443Updated Jul 17, 2025Jul 17, 2025
    • Spike, a RISC-V ISA Simulator
      C
      9502.8k29749Updated Jul 17, 2025Jul 17, 2025
    • Mirror of FSL. Fusion/Fracture Specification Language.
      C++
      0000Updated Jul 14, 2025Jul 14, 2025
    • Mirror of STF Library. The acronym STF stands for Simulation Trace Format. This is intended to be used with Sparta-based simulators, but that's not necessary.
      C++
      0000Updated Jul 14, 2025Jul 14, 2025
    • Mirror of Mavis. Mavis is a framework that allows decoding of the RISC-V ISA into custom instruction class types as well as custom extensions to those class types.
      C++
      0000Updated Jul 14, 2025Jul 14, 2025
    • RISC-V Boot and Runtime Services Test Suite
      C
      5200Updated Jul 11, 2025Jul 11, 2025
    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      5891.2k833Updated Jun 30, 2025Jun 30, 2025
    • riscv-pk

      Public
      RISC-V Proxy Kernel
      C
      324645855Updated Jun 20, 2025Jun 20, 2025
    • C
      5051k12024Updated Jun 13, 2025Jun 13, 2025
    • librpmi

      Public
      Reference implementation of RPMI specification as a library.
      C
      111030Updated May 6, 2025May 6, 2025
    • RISC-V Configuration Validator
      Python
      55791918Updated Mar 28, 2025Mar 28, 2025
    • riscof

      Public
      Python
      46835715Updated Mar 28, 2025Mar 28, 2025
    • riscv-isac

      Public archive
      Python
      5533199Updated Nov 4, 2024Nov 4, 2024
    • riscv-ctg

      Public archive
      Python
      5242128Updated Nov 4, 2024Nov 4, 2024
    • homebrew (macOS) packages for RISC-V toolchain
      Ruby
      5534793Updated Oct 26, 2024Oct 26, 2024
    • Toolchains, scripts, and workloads to analyze proposed instructions as part of the Scalar Efficiency SIG.
      Ruby
      0000Updated May 30, 2024May 30, 2024
    • riscv-tools

      Public archive
      RISC-V Tools (ISA Simulator and Tests)
      Shell
      4491.2k1043Updated Dec 22, 2022Dec 22, 2022
    • A docker image for building RISC-V documentation
      Dockerfile
      3300Updated Sep 15, 2022Sep 15, 2022
    • template-riscv-code

      Public template
      This repository will be cloned for new RISC-V (only) code projects
      0000Updated Aug 10, 2022Aug 10, 2022
    • .github

      Public
      0000Updated Jul 1, 2022Jul 1, 2022
    • The Software Overlay TG will specify the requirements for the software overlay feature, both from the FW manager engine and from toolchain aspects, all which will be based on the current RISC-V ISA and extensions.
      C
      51411Updated May 24, 2022May 24, 2022
    • JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
      JavaScript
      6234771Updated Aug 25, 2020Aug 25, 2020