v0.39.9

Added

• assign: Add assignment to flat axi ports. #392
• Add axi_inval_filter. #386

Fixed

• axi_to_detailed_mem: Avoid spurious write responses with HideStrb. #383
• axi_dw_downsizer: Fix linting warnings. #385
• axi_burst_unwrap: Remove overly pessimistic assertion. #387
• axi_burst_splitter_gran: Ensure IP has stable w.last. #393
• axi_fifo_delay_dyn_intf: Use DELAY_WIDTH for delay ports. #395
• axi_to_mem: Fix strb inputs to dead_response_fifo. #389
• axi_id_prepend: Fix implicit conversion linter warning. #397

Changed

• axi_burst_unwrap: Only invalidate WRAP bursts if they are unmodifiable. #382

v0.39.8

Added

• Add a non-synthesizable IP to delay each channel of an AXI bus individually. #380
• Add granular version of the burst_splitter, originally developed for AXI-Realm. #377
• Add linting pass to CI elaborating with Verilator. #378

Fixed

• axi_burst_splitter: Fix address alignment issues. #375
• axi_lite_to_apb: Various fixes. #375
• axi_to_mem: Fix edge cases. #376
• Various lint fixes. #374
  `

Changed

• axi_sim_mem: Propagate user field on B and R channels. #373
• Switched to VSIM version 2025.1 in CI. #378

v0.39.7

0.39.7 - 2025-05-20

Added

• Add axi_burst_unwrap. #326

Fixed

• Modify axi_dw_upsizer to avoid unnecessarily wide indices into r_data. #362
• [test] Remove begin/end from constructors to fix morty ci err
• axi_lite_lfsr: Add missing signal declaration. (#363)
• axi_to_mem_interleaved: Fix busy signal.
• axi_dw_downsizer: Fix unnecessarily wide indices for verilator compatibility. #366

Changed

• Add random user signal generation for llc-partition test. #315
• Update common_verification from v0.2.4 to v0.2.5.
• Add selective channel bypassing to axi_cut.

v0.39.6

0.39.6 - 2024-12-04

Added

• Support connectivity in axi_intercon_gen. #351
• Add iomsb function to avoid underflow in array lengths to axi_pkg. #355

Fixed

• Make the case statements in axi_dw_upsizer unique. Add default cases to prevent simulator warnings. #348
• Fix write channel assertions in axi_rw_split. #357
• Tie unused demux port in pass-through termination in axi_isolate. #359

Changed

• Improve VCS and Verilator support treewide. #358
• Update common_verification to v0.2.4 to include Verilator fixes.

v0.39.5

0.39.5 - 2024-10-24

Fixed

• Disabled the interface variant of axi_xbar_unmuxed for VCS, as VCS does not support multi-dimensional arrays of interfaces yet.

Changed

• axi_id_serialize: Revert #342 to fix boot problems of CVA6 in Cheshire.

v0.39.4 (Yanked)

0.39.4 - 2024-07-25 (Yanked 2024-10-24)

Caution

This release was yanked due to a bug in the axi_id_serialize module. PLEASE DO NOT USE THIS RELEASE.

Added

• axi_sim_mem: Increase number of request ports, add multiport interface variant.
• axi_bus_compare: Optionally consider AXI size field to only compare used data.
• AXI_BUS_DV: Add property checking that bursts do not cross 4KiB page boundaries.
• Add axi_xbar_unmuxed: Partial crossbar with unmultiplexed mst_ports.

Fixed

• axi_bus_compare: Fix mismatch detection.
• axi_to_detailed_mem: Only respond with exokay if lock was set on the request.
  Bump common_cells for mem_to_banks fix.
• axi_dw_downsizer: Fix i_forward_b_beats_queue underflow.
• axi_atop_filter: Add reset state to internal FSM to avoid simulation bug in XSIM.
• axi_test: Ensure random requests do not cross 4KiB page boundaries.

Changed

• axi_id_serializer: Change internal design (and behavior) for simpler code, less hardware, and
  less stalling.

v0.39.4 is fully backward-compatible to v0.39.3.

v0.39.3

0.39.3 - 2024-05-08

Added

• axi_sim_mem: Allow response data for uninitialized region to have configurable defined value.
• axi_test: add clear_memory_regions to axi_rand_master.
• axi_test: Add add_traffic_shaping_with_size to axi_rand_master to allow for traffic shaping
  with a custom size.

Changed

• axi_pkg: Adjust LatencyMode parameter of xbar_cfg_t to bit vector from xbar_pipeline_e
  enum to allow custom configurations.

v0.39.3 is fully backward-compatible to v0.39.2.

v0.39.2

0.39.2 - 2024-03-13

Added

• axi_interleaved_xbar: An experimental crossbar extension interleaving memory transfers over #334
  subordinate devices. Use at your own risk.
• axi_zero_mem: Implementing \dev\zero function for AXI. #334

Fixed

• axi_to_detailed_mem: VCS crashed on default parameters 0, changed them to 1 #334
• axi_to_mem: Add missing testmode pins #327
• axi_sim_mem: Fix byte calculation in R and W forks #331

v0.39.2 is fully backward-compatible to v0.39.1.

v0.39.1

Added

• axi_cdc: Add SyncStages parameter.
• axi_to_mem_interleaved: Add interface variant.
• axi_burst_splitter: Expose id_queue's FULL_BW parameter.
• axi_chan_compare: Add parameter to allow reordered transactions.
• Add AXI_HIGHLIGHT macro to highlight AXI signals.
• Add flat port instantiation macros.

Fixed

• axi_test: Avoid false negatives for misaligned reads in axi_scoreboard.
• axi_to_detailed_mem: Ensure proper propagation or err and exokay signals.

v0.39.0

Added

• Synthesizable IPs:
  • axi_bus_compare and axi_slave_compare; two synthesizable verification IPs meant to be used
    to compare two AXI buses on an FPGA.
  • axi_lite_from_mem and axi_from_mem acting like SRAMs making AXI4 requests downstream.
  • axi_lite_dw_converter: Convert the data width of AXI4-Lite transactions. Emits the
    appropriate amount of downstream transactions to perform the whole requested access.
  • axi_rw_join and axi_rw_split to split/join the read and write channels of an AXI bus.
• CT-macros allowing to instantiate AXI structs with custom channel type names.
• axi_pkg': Add documentation to xbar_cfg_t`.
• Testbench IPs:
  • axi_chan_compare.sv: Non-synthesizable module comparing two AXI channels of the same type
  • Add axi_file_master to axi_test, allowing file-based AXI verification approaches.
  • Add #_width functions to axi_test returning the width of the AXI channels.

Changed

• Synthesizable IPs:
  • axi_demux: Replace FIFO between AW and W channel by a register plus a counter. This prevents
    AWs from being issued to one master port while Ws from another burst are ongoing to another
    master port. This is required to prevents deadlocks due to circular waits downstream. Removes
    FallThrough parameter from axi_demux.
  • Split the axi_demux logic and timing decoupling. A new module called axi_demux_simple contains
    the core logic.
  • axi_dw_downsizer uses axi_pkg::RESP_EXOKAY as a default value.
  • Simplify the casez in axi_id_remap.
  • Add optional explicit mapping to the axi_id_serialize module.
  • Expand axi_to_mem to axi_to_detailed_mem exposing all of AXI's side-signals; namely id, user,
    cache, prot, qos, region, atop. Add possibility to inject err and exokay.
  • axi_xbar: Add parameter PipelineStages to axi_pkg::xbar_cfg_t. This adds axi_multicuts
    in the crossed connections in the xbar between the demuxes and muxes. Improve inline
    documentation.
  • Move mem_to_banks to common_cells.
• axi_pkg: Improve for better compatibility with Vivado.
• `axi_test:
  • axi_lite_rand_slave: R response field is now randomized.
  • Remove excessive prints from random master and slave.
  • Properly size-align the address.
• axi_pkg: Define localparams to define AXI type widths.
• Update common_cells from version v1.26.0 to v1.27.0.
• Tooling:
  • Use pulp-platform/pulp-actions/gitlab-ci@v2 in the GitHub CI to communicate with the internal CI.
  • Bump DC Shell version from 2019.12 to 2022.03
  • No longer check ModelSim versions 10.7e and 2021.3, add 2022.3.
  • More thorough verification runs for the xbar.
  • Start transitioning from shell script to Makefile to run simulations.
• Use scripts/update_authors to update authors, slight manual fixes performed.

Fixed

• axi_to_mem_banked: Reduce hardware by properly setting UniqueIds.
• axi_to_mem_interleaved and axi_to_mem_split properly instantiates a demultiplexer now.
  Adds test_i port for DFT.

Breaking Changes

There are breaking changes between v0.38.0 and v0.39.0:

• axi_demux: FallThrough parameter was removed.
• axi_xbar: axi_pkg::xbar_cfg_t added PipelineStages parameter.
• axi_to_mem_interleaved and axi_to_mem_split: Added test_i input port.