Fix HS400 on CM5 #6203
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Fix HS400 on CM5 #6203
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The attached PHY performs parameter validation, so the switch from HS200 to HS (before selecting HS400/HS400es) with a 200MHz clock fails to update pad timings and results in CRC errors from the card. Underclocking the interface is safe, so do that in the downgrade callback. Signed-off-by: Jonathan Bell <[email protected]>
Now that we've figured out why the PHY didn't do the right thing, HS400 is stable again. This reverts commit 6aeacfc. Signed-off-by: Jonathan Bell <[email protected]>
Enhanced strobe means HS200 training can be skipped. Signed-off-by: Jonathan Bell <[email protected]>
SD cards perform cache flushes by a CMD49 extension register write - which needs to be started from the SDHCI command/argument registers and not a CQHCI slot. Host access to SD/CQ registers should be exclusive to one or the other, so issue a halt before doing the command. Signed-off-by: Jonathan Bell <[email protected]>
This gains about 8-12% sequential write speed with the fastest SD/eMMC cards, and Class A1/A2 card sequential performance is only assured with a 4MiB write length. Signed-off-by: Jonathan Bell <[email protected]>
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@timg236 this works for me on both r0.1 and r0.2 boards. |
popcornmix
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kernel: Fix HS400 on CM5 See: raspberrypi/linux#6203 kernel: Reinstate "output format" DRM property See: raspberrypi/linux#6133 kernel: Fix the IQaudIO handling of 16-bit samples See: raspberrypi/linux#6215
popcornmix
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Jun 12, 2024
kernel: Fix HS400 on CM5 See: raspberrypi/linux#6203 kernel: Reinstate "output format" DRM property See: raspberrypi/linux#6133 kernel: Fix the IQaudIO handling of 16-bit samples See: raspberrypi/linux#6215
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CM5 HS400 is now reliable for me.
Also found two more commits for SD down the back of the sofa...