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Pin revision, potentially less cross-over on the bottom part of the chip
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3 files changed

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‎src/ci2406_z80.v

Lines changed: 44 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module ci2406_z80(
4040
// 2) Z80 data bus pin order is "scrambled"
4141

4242
// Z80 CPU
43+
// 1st attempt:
4344
// ,----------------.___.----------------.
4445
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
4546
// <-- A12 |2 - io[20] 58 54 io[17] - 39| A9 -->
@@ -63,6 +64,31 @@ module ci2406_z80(
6364
// <-- /IORQ |20 - io[4] 35 36 io[5] - 21| /RD -->
6465
// `-------------------------------------'
6566
//
67+
68+
// 2nd revised:
69+
// ,----------------.___.----------------.
70+
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
71+
// <-- A12 |2 - io[20] 58 54 io[17] - 39| A9 -->
72+
// <-- A13 |3 - io[21] 59 53 io[16] - 38| A8 -->
73+
// <-- A14 |4 - io[22] 60 51 io[15] - 37| A7 -->
74+
// <-- A15 |5 - io[23] 61 >50 io[14] - 36| A6 -->
75+
// --> CLK |6 - xclk 22-- >48 io[13] - 35| A5 -->
76+
// <-> D4 |7 - io[24] 62< 46 io[12] - 34| A4 -->
77+
// <-> D3 |8 - io[25] 2< 45 io[11] - 33| A3 -->
78+
// <-> D5 |9 - io[26] 3 44 io[10] - 32| A2 -->
79+
// <-> D6 |10 - io[27] 4 43 io[9] - 31| A1 -->
80+
// VCC_5V0 |11 42 io[8] - 30| A0 -->
81+
// <-> D2 |12 - io[28] 5 29| GND
82+
// <-> D7 |13 - io[29] 6 41 io[7] - 28| /RFSH -->
83+
// <-> D0 |14 - io[30] 7 --33 io[2] - 27| /M1 -->
84+
// <-> D1 |15 - io[31] 8 --21 rst - 26| /RESET <--
85+
// --> /INT |16 - io[32] 11 * 37 io[6] - 25| /BUSRQ <--
86+
// --> /NMI |17 - io[33] 12 * 36 io[5] - 24| /WAIT <--
87+
// <-- /HALT |18 - io[0] 31-- --32 io[1] - 23| /BUSAK -->
88+
// <-- /MREQ |19 - io[34] 13 * * 35 io[4] - 22| /WR -->
89+
// <-- /IORQ |20 - io[35] 14<* * 34 io[3] - 21| /RD -->
90+
// `-------------------------------------'
91+
//
6692
// GND 29 --- vss* [56,52,38,39,29,23,20,10,1]
6793
// VCC_5V0 11 --- vddio [64,17]
6894
// VCC_3V3 xx --- vdda1, vdda2 [47,40,30,9]
@@ -72,25 +98,28 @@ module ci2406_z80(
7298
// @TODO: float A, D, MREQ, RD, WR, IORQ pins on BUSAK (Figure 10 BUS Request/Acknowledge Cycle)
7399

74100
// 8 output control pins
75-
assign io_oeb[7:0] = {8{1'b0}}; // 0 = Output
101+
assign {io_oeb[35:34], io_oeb[7], io_oeb[4:0]}
102+
= { 8{1'b0}}; // 0 = Output
103+
76104
// 16 output address bus pins
77-
assign io_oeb[23:8] = {16{1'b0}}; // 0 = Output
105+
assign io_oeb[23:8] = {16{1'b0}}; // 0 = Output
106+
78107
// 8 bidirectional data bus pins
108+
assign io_oeb[31:24] = {8{~data_oe}};// 0 = Output | 1 = Input
79109

80-
assign io_oeb[31:24] = {8{~data_oe}}; // 0 = Output | 1 = Input
81110
// 4 input control pins
82-
assign io_oeb[35:32] = {4{1'b1}}; // 1 = Input
83-
assign io_out[35:32] = {4{1'b0}}; // Initialize otherwise undriven pins to 0
111+
assign {io_oeb[33:32], io_oeb[6:5]} = { 4{1'b1}}; // 1 = Input
112+
assign {io_out[33:32], io_out[6:5]} = { 4{1'b0}}; // Initialize otherwise undriven pins to 0
84113

85114
wire data_oe;
86115
z80 z80 (
87116
.clk (z80_clk),
88117
.cen (ena),
89118
.reset_n (rst_n),
90-
.wait_n (io_in [34]),
119+
.wait_n (io_in [ 5]),
91120
.int_n (io_in [32]),
92121
.nmi_n (io_in [33]),
93-
.busrq_n (io_in [35]),
122+
.busrq_n (io_in [ 6]),
94123
// Z80 has peculiar data bus pin order, keep it to minimize wire crossing on the DIP40 PCB
95124
// Also see: http://www.righto.com/2014/09/why-z-80s-data-pins-are-scrambled.html
96125
// D7 - io[29]
@@ -105,14 +134,14 @@ module ci2406_z80(
105134
.dout ({io_out[29], io_out[27], io_out[26], io_out[24], io_out[25], io_out[28], io_out[31], io_out[30]}),
106135
.doe (data_oe),
107136
.A (io_out[23:8]),
108-
.halt_n (io_out[0]),
109-
.busak_n (io_out[1]),
110-
.m1_n (io_out[2]),
111-
.mreq_n (io_out[3]),
112-
.iorq_n (io_out[4]),
113-
.rd_n (io_out[5]),
114-
.wr_n (io_out[6]),
115-
.rfsh_n (io_out[7])
137+
.halt_n (io_out[ 0]),
138+
.busak_n (io_out[ 1]),
139+
.m1_n (io_out[ 2]),
140+
.mreq_n (io_out[34]),
141+
.iorq_n (io_out[35]),
142+
.rd_n (io_out[ 3]),
143+
.wr_n (io_out[ 4]),
144+
.rfsh_n (io_out[ 7])
116145
);
117146
endmodule
118147

‎test_chipignite/tb.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,10 @@ module tb ();
2020
wire [35:0] io_oeb;
2121

2222
wire [3:0] controls_in;
23-
wire [7:0] controls_out = io_out[7:0];
23+
wire [7:0] controls_out = {io_out[35:34], io_out[7], io_out[4:0]};
2424
wire [15:0] addr = io_out[23:8];
2525

26-
assign io_in [35:32] = controls_in;
26+
assign {io_in [33:32], io_in [6:5]} = controls_in;
2727

2828
// Z80 has a peculiar order of the pins for the data bus
2929
// <-> D4 | io[24]

‎test_chipignite/test.py

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
from cocotb.clock import Clock
66
from cocotb.triggers import ClockCycles, FallingEdge, RisingEdge
77

8-
BUS_READY = 0b1111 # not WAIT, not INT, not NMI, not BUSRQ
8+
BUS_READY = 0b1111 # not WAIT, not BUSRQ, not INT, not NMI
99
OPCODE_NOP = 0x00
1010
OPCODE_LDHL = 0x21
1111
OPCODE_LDNNA = 0x32
@@ -150,16 +150,19 @@ async def start_and_reset(dut):
150150
async def z80_step(z80, cycle, verbose=False):
151151
def read_controls():
152152
controls = [bit_n(z80.controls_out, n) for n in range(8)]
153-
return dict(zip(['halt', 'busak', 'm1', 'mreq', 'ioreq', 'rd', 'wr', 'rfsh'], controls))
154153
# | 41 io[7] - 28| /RFSH -->
155154
# | 33 io[2] - 27| /M1 -->
156155
# | |
157156
# | |
158157
# | |
159158
# <-- /HALT |18 - io[0] 31 32 io[1] - 23| /BUSAK -->
160-
# <-- /MREQ |19 - io[3] 34 37 io[6] - 22| /WR -->
161-
# <-- /IORQ |20 - io[4] 35 36 io[5] - 21| /RD -->
159+
# <-- /MREQ |19 - io[34] 13 35 io[4] - 22| /WR -->
160+
# <-- /IORQ |20 - io[35] 14 34 io[3] - 21| /RD -->
162161
# `-------------------------------------'
162+
#
163+
# io[0] io[1] io[2] io[3] io[4] io[7] io[34] io[35]
164+
return dict(zip(['halt', 'busak', 'm1', 'rd', 'wr', 'rfsh', 'mreq', 'ioreq'], controls))
165+
163166
def read_data():
164167
if z80.data_oe.value != 0b1111_1111:
165168
return 'ZZ'

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