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New attribute: Tag_RISCV_reserved_register #195
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The stuff about the register lists is a little confusing, as the encoding chosen for Tag_RISCV_reserved_register requires a bit vector. So I think you might be talking about the acceptable assembly input, or objdump/readelf output. But not the encoding in the object file. This is a little unclear the way it is worded. Maybe add something about human readable input/output can use the alternate syntax. Also not clear if this is the right place to document assembly syntax. Maybe that should be in the asm manual? Otherwise this looks reasonable to me. |
Given custom extensions start at 3072 this doesn't make sense in the current form IMO. |
Also, a file without the tag being merged with a file with the tag is just asking for trouble. |
Your grammar also parses ambiguously as you have REG_LIST on either side of the comma, even though the "operator" is associative so it doesn't really matter. I'd be inclined to express it as:
and maybe also add |
riscv-elf.md
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@@ -1043,6 +1043,7 @@ Tag_RISCV_unaligned_access | 6 | uleb128 | Indicates whet | |||
Tag_RISCV_priv_spec | 8 | uleb128 | Indicates the major version of the privileged specification. | |||
Tag_RISCV_priv_spec_minor | 10 | uleb128 | Indicates the minor version of the privileged specification. | |||
Tag_RISCV_priv_spec_revision | 12 | uleb128 | Indicates the revision version of the privileged specification. | |||
Tag_RISCV_reserved_register | 14 | uleb128 | Indicates the extra reserved register information. |
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Should be plural
My thought is provide some flexible for human written asm file, but I admit that could be a trouble, I think in future we might add an extra asm directive to make this thing easier (e.g. I'll update that later to remove the exception merge rule. |
Thanks for the review comment, split human readable input/output part to asm manual sounds good to me, we don't have any word for |
I have a patch for LLVM which implements this here: D113890 This is needed in order to reserve registers for use by the overlay engine. |
I have a branch of my own which tries to incorporate the feedback from here (also a rebase). I can turn this into a pull request of its own if that's best? https://github.com/edward-jones/riscv-elf-psabi-doc/tree/erj-reserved-register-attr I agree that the assembler syntax/human readable format should be in the assembler manual. As for the merging of objects files with/without the tag, I think best to disallow mixing entirely and then an option could be added later to explicitly supress that warning in cases where you're deliberately linking object files with different tags. |
- Motivation: Tag_RISCV_reserved_register used for record reserved register information, desiged for resolve checking compatibility between ABI subvariants like overlay ABI. - Meaning: This attribute is a bit-vector of reserved register, syntax for assembly language please refer https://github.com/riscv-non-isa/riscv-asm-manual . - Merge Rule: It will report errors if link object files with different Tag_RISCV_reserved_register values, but allowed link with object with and without Tag_RISCV_reserved_register value, the final value will take from the object which has set Tag_RISCV_reserved_register.
- The attribute name is plural now, Tag_RISCV_reserved_registers - Make the distinction between the encoded value and the human readable syntax a bit clearer. - Remove ambiguity from the grammar for the tag based on feedback. - Add possibility for an empty register list to the grammar - Remove the exception allowing merging of two objects files if one includes the tag and the other doesn't
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Can I ask what the path forward is for this. In the psABI call someone (I can't remember who?) suggested that there may be a simpler solution for the overlay system, but I don't think they elaborated on what the solution was? |
IIRC Anders Berg (from IAR) said, he will give move detail next time. |
The PR is important for Overlay, but it is a generic solution for saving registers + the option to validate register usage between libs on link time. We don't see any correlation between this PR and the "helper functions" or in a future new ABI. |
Hi Ofer: The policy for psABI is we won't merge anything new stuffs before releasing 1.0, however I guess that might take another 2 or 3 month due to the release process, so I think maybe we could branch out 1.0, and then keep including new stuffs for master branch, however that need to discuss with @jrtc27 and @cmuellner in next Toolchain & Runtime TS Bi-Weekly Meeting (2/14). |
Hi Kito,
Seem like a good idea to branch changes after 1.0.
Thanks,
Ofer
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Subject: Re: [riscv-non-isa/riscv-elf-psabi-doc] New attribute: Tag_RISCV_reserved_register (#195)
Hi Ofer:
The policy for psABI is we won't merge anything new stuffs before releasing 1.0, however I guess that might take another 2 or 3 month due to the release process, so I think maybe we could branch out 1.0, and then keep including new stuffs for master branch, however that need to discuss with @jrtc27<https://github.com/jrtc27> and @cmuellner<https://github.com/cmuellner> in next Toolchain & Runtime TS Bi-Weekly Meeting (2/14).
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Temporarily forking the document risks leading to confusion, but even if that weren't an issue, handling things other than those for 1.0 takes away precious time from getting the release out the door. Let's just focus on what we need to rather than getting distracted by future things, especially those that are quite subjective like this. |
@jrtc27 : So maybe we could give a label (maybe |
Reserving relocation numbers requires reaching a consensus that the set of relocations is correct. I do not want to waste what little time I have pushing forward non-1.0 things. |
Motivation
Tag_RISCV_reserved_register used for record reserved register information,
desiged for resolve checking compatibility between ABI subvariants like
overlay ABI.
Meaning
This attribute is a bit-vector of reserved register, but it can also
representation as a register list, syntax below:
For example:
x6
,x7
,x8
andf10
are reserved, then the value ofTag_RISCV_reserved_register is
0x400000001c1
, and it also could be representas
{x6, x7, x8, f10}
or{x6-x8, f10}
.Merge Rule
It will report errors if link object files with different
Tag_RISCV_reserved_register values, but allowed link with object with and
without Tag_RISCV_reserved_register value, the final value will take from the
object which has set Tag_RISCV_reserved_register.