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Clarify implications for fcsr #288
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I am struggling with
Just make sure you are trying to address this by following sentence ?
Agree with that, thanks! |
Another attempt to clarify fcsr: #289 |
My understanding is that the ISA guarantees that each hardware thread (hart) will have its own
Correct. |
As far as I can tell, neither Clang nor GCC fully supports My attitude is that my use-case would be better addressed by F-extension intrinsics. I acknowledge that this is a RISC-V-specific solution; however, in my experience, the people asking for this functionality generally aren't writing code that is meant to be broadly portable across architectures. Another one of my objectives with this PR is to leave the psABI open to eventual implementation of |
Yeah, that's one reason I didn't mention FENV_ACCESS in #289 since I am not sure should we mention a thing without well implemented in mainstream open source compilers...
Might be little bit digress from the topic, but I am curious what the shape is for those intrinsic in your mind? providing static rounding mode argument? or guarantee the order among different F-ext. intrinsic? |
My understanding is that the psABI intends for
fcsr
to be the ABI manifestation offenv
, when the latter is relevant. With this understanding, I find the current wording to be misleading:fcsr
is an object in the ISA, not the C language, so it is nonsensical to say it has "thread storage duration".fcsr
for all programs, even those that don't access/modifyfenv
.fenv
have been present since C99, so the specific reference to C11 is not meaningful.This PR attempts to clarify the intent while addressing these three points. Your feedback is most welcome.