Merge pull request #68 from pathakraul/rpmi_updates

Improvements and Formatting changes in service groups

src/srvgrp-clock.adoc

@@ -11,12 +11,12 @@ endif::rootpath[]
 
 ===  Service Group - CLOCK (SERVICEGROUP_ID: 0x0007)
 This service group is for the management of system clocks. Services defined in
-this group are used to enable or disable clocks, and to set/get clock rates.
+this group are used to enable or disable clocks, and to set or get clock rates.
 
-Each clock in the system is identified by the clock ID, which is an integer
-identifier assigned to each clock. The mapping of CLOCK_ID and clock is known
-to both the application processor and the platform microcontroller. Clock ID
-identifiers are sequential and starting from `0`.
+Each clock in the system is identified by the clock ID, which is an 32-bit
+integer identifier assigned to each clock. The mapping of CLOCK_ID and clock is
+known to both the application processor and the platform microcontroller.
+Clock ID identifiers are sequential and starting from `0`.
 
 The device or the group of devices sharing the same clock source form a
 single clock domain, which is identified by the CLOCK_ID. Any change to the
@@ -76,12 +76,18 @@ Each clock rate is a array of two 32-bit values `(uint32, uint32)` represented
 as `(clock_rate_low, clock_rate_high)` and packed in the same order where
 `clock_rate_low` is at the lower index than the `clock_rate_high`.
 
-* Discrete Clock Format
-
+===== Discrete Clock Format
 A set of discrete clock rate arranged in a sequence, starting from the
 lowest value at the lowest index and increasing sequentially to higher clock
 rate. The following table shows the structure of the Discrete clock format.
 
+```c
+[clock_rate1, clock_rate2, clock_rate3, ... , clock_rateN]
+
+where:
+clock_rate1 < clock_rate2 < clock_rate3, < ... < clock_rateN
+```
+
 .Discrete Clock Format Structure
 [cols="1,2,5" width=100%, align="center", options="header"]
 |===
@@ -98,11 +104,14 @@ rate. The following table shows the structure of the Discrete clock format.
 | Upper 32-bit clock rate in Hz.
 |===
 
-* Linear Clock Format
-
+===== Linear Clock Format
 A linear range of clock rate with a constant step size.
 The following table shows the structure of the Linear clock format.
 
+```c
+[clock_rate_minimum, clock_rate_maximum, clock_step]
+```
+
 .Linear Clock Format Structure
 [cols="1,3,5" width=100%, align="center", options="header"]
 |===
@@ -111,27 +120,27 @@ The following table shows the structure of the Linear clock format.
 | Description
 
 | 0
-| MIN_CLOCK_RATE_LOW
+| CLOCK_MIN_RATE_LOW
 | Lower 32-bit of the lowest clock rate in Hz.
 
 | 1
-| MIN_CLOCK_RATE_HIGH
+| CLOCK_MIN_RATE_HIGH
 | Upper 32-bit of the lowest clock rate in Hz.
 
 | 2
-| MAX_CLOCK_RATE_LOW
+| CLOCK_MAX_RATE_LOW
 | Lower 32-bit of the highest clock rate in Hz.
 
 | 3
-| MAX_CLOCK_RATE_HIGH
+| CLOCK_MAX_RATE_HIGH
 | Upper 32-bit of the highest clock rate in Hz.
 
 | 4
-| STEP_LOW
+| CLOCK_STEP_LOW
 | Lower 32-bit of the step between two successive rates in Hz.
 
 | 5
-| STEP_HIGH
+| CLOCK_STEP_HIGH
 | Upper 32-bit of the step between two successive rates in Hz.
 |===
 

src/srvgrp-cppc.adoc

@@ -88,7 +88,8 @@ and faster read of the performance feedback values supported over the
 fast-channel.
 
 The CPPC service group defines two types of fast-channel for each application
-processor.
+processor. If fast-channels are supported then each application processor must 
+be assigned both types fast-channel. 
 
 ===== Performance Request Fast-channel
 In this fast-channel the application processor will either write
@@ -162,11 +163,11 @@ The size of this fast-channel type is `8 bytes`.
 | Current frequency high 32-bit (Hz)
 |===
 
-If fast-channels are supported then each application processor must be assigned
-both types fast-channel. In the shared memory region allocated by the
-platform for fast-channels, the Performance Request fast-channels must be grouped
-together for all the application processors. Similarly, the Performance Feedback
-fast-channels must be grouped together.
+===== CPPC Fast-channel Shared Memory Region
+In the shared memory region allocated by the platform for fast-channels, the
+Performance Request fast-channels must be grouped together for all the
+application processors. Similarly, the Performance Feedback fast-channels must
+be grouped together.
 
 The size of the shared memory region for fast-channels for all the managed
 application processors must be a `power-of-2`. The `base-address` and `size`
@@ -175,12 +176,12 @@ service `CPPC_GET_FAST_CHANNEL_REGION`. The `base-address` of the shared memory
 region must be aligned to `8 bytes` which is maximum size of a fast-channel in
 both the types.
 
-The offsets of fast-channel of both types for an application processor are aligned
-to `8 bytes`. The offset of both fast-channel types in the shared memory region can
-be discovered through service `CPPC_GET_FAST_CHANNEL_OFFSET`. The offsets
-discovered can be added into the `base-address` of the shared memory region to
-form the address of Performance Request fast-channel and Performance Feedback
-fast-channel for an application processor.
+The offsets of fast-channel of both types for an application processor are
+aligned to `8 bytes`. The offset of both fast-channel types in the shared memory
+region can be discovered through service `CPPC_GET_FAST_CHANNEL_OFFSET`. The
+offsets discovered can be added into the `base-address` of the shared memory
+region to form the address of Performance Request fast-channel and Performance
+Feedback fast-channel for an application processor.
 
 ===== Performance Request Fast-channel Doorbell
 A doorbell can also be supported for this fast-channel type which is shared

src/srvgrp-device-power.adoc

@@ -12,7 +12,7 @@ endif::rootpath[]
 ===  Service Group - DEVICE_POWER (SERVICEGROUP_ID: 0x0008)
 This DEVICE_POWER service group provides messages to manage the power states of
 a device power domain. This service group is used only for device power
-management since System and CPU power management is handled by already defined
+management since system and CPU power management is handled by already defined
 service groups such as SYSTEM_RESET, SYSTEM_SUSPEND and HART_STATE_MANAGEMENT.
 
 A domain can consist of one device if its power states can be controlled
@@ -29,7 +29,7 @@ lost information corresponding to that state.
 
 The DEVICE_POWER services take a 32-bit integer identifier known as `DOMAIN_ID`
 to specify the device power domain. These `DOMAIN_ID` identifiers are sequential
-and start from 0.
+and start from `0`.
 
 The following table lists the services in the DEVICE_POWER service group:
 
@@ -267,7 +267,7 @@ This service is used to query the attributes of a device power domain.
 | _Reserved_ and must be `0`.
 
 | 2
-| TRANS_LATENCY
+| TRANSITION_LATENCY
 | uint32
 | Worst case transition latency of domain from one power state to another, in microseconds (us).
 

src/srvgrp-performance.adoc

@@ -19,9 +19,9 @@ scale represents a performance operating point. What this scale represents and
 the metric is entirely platform-dependent. Values on this scale are discrete,
 and the platform has complete control over mapping these performance operating
 points to performance states, which are eventually converted into hardware
-parameters such as voltages and frequencies. For example, the mapping between
+parameters such as voltage and frequency. For example, the mapping between
 levels and frequencies can be as straightforward as using a multiplication
-factor of 1000.
+factor of `1000`.
 
 The CPPC service group is designed for performance control, but it is only
 intended for application processors. This service group is primarily meant for