Search results

Interaction of cbo.inval with mprv

Status: Open.

#70 In riscv/riscv-CMOs;

· vishmohan opened on Jan 13, 2025

prefetch i/r/w encoding overlaps with ORI instr

Status: Open.

#68 In riscv/riscv-CMOs;

· akifejaz opened on Oct 20, 2024

Interaction between management instructions and dirty bit

Status: Open.

#45 In riscv/riscv-CMOs;

· jrtc27 opened on Dec 18, 2021

Use cases for CMOs - collect

Status: Open.

#15 In riscv/riscv-CMOs;

· AndyGlew opened on Sep 28, 2020

FOURTH QUESTION: How do we specify which parts of the memory/cache hierarchy are affected by CMOs ?

Status: Open.

#12 In riscv/riscv-CMOs;

· AndyGlew opened on Sep 2, 2020

SECOND QUESTION: cache index CMOs, e.g. (set,way) vs "microarchitecture index range"

Status: Open.

#10 In riscv/riscv-CMOs;

· AndyGlew opened on Sep 2, 2020

FIRST BIG QUESTION: Address Range vs per-Cache-Line CMO instructions

Status: Open.

#9 In riscv/riscv-CMOs;

· AndyGlew opened on Sep 2, 2020

Don't assume cache line sizes are fixed during program execution

Status: Open.

#8 In riscv/riscv-CMOs;

· brucehoult opened on Sep 1, 2020