Merge pull request #43 from ved-rivos/0622_2

update SRET and MRET behavior for clearing xDT

src/riscv-double-trap.adoc

@@ -133,7 +133,9 @@ taken into M-mode. The `mtval2` register is then set to what would be otherwise
 written into the `mcause` register by the _unexpected trap_. The `mcause`
 register is set to 16, the double-trap exception code.
 
-An `SRET` instruction sets the `SDT` bit to 0.
+When executing in S-mode, the `SRET` instruction sets `sstatus.SDT` to 0, and
+when executing in VS-mode, it sets `vsstatus.SDT` to 0. If the new privilege
+mode is less privileged than VS-mode, it also sets `vsstatus.SDT` to 0.
 
 [NOTE]
 ====
@@ -220,7 +222,9 @@ are platform-specific. The range of possible actions include restarting
 the affected hart or restarting the entire platform, among others.
 ====
 
-The `MRET` and `SRET` instructions set the `MDT` bit to 0.
+The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit
+to 0. If the new privilege mode is less privileged than S/HS-mode, `sstatus.SDT`
+is set to 0. If it is less privileged than VS-mode, `vsstatus.SDT` is set to 0.
 
 The Smdbltrp extension introduces a read-write critical-error-trigger (`cetrig`)
 field (bit 19) to the `dcsr` CSR cite:[DBG]. When `cetrig` is set to 1, a hart