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Should xithreshold be cleared when returning from ISR
#540
opened Jun 2, 2025 by
christian-herber-nxp
The smclicshv extension naming (i.e. sm*) suggests it only has M-mode features but it affects S-mode and has one S-mode CSR bit
reorg
Reorganization for Priv ISA manual integration
v1.0
resolve for 1.0
#421
opened Sep 30, 2024 by
james-ball-qualcomm
Add optional support for hardware register save e.g. shadow register sets?
post-v1.0
To be handled after v1.0
#329
opened Apr 23, 2023 by
brucehoult
Hypervisor mode should be discussed.
post-v1.0
To be handled after v1.0
#248
opened Jun 21, 2022 by
kasanovic
Allow mix of CLIC/CLINT at different privilege modes
post-v1.0
To be handled after v1.0
#192
opened Jan 18, 2022 by
kasanovic
ProTip!
Updated in the last three days: updated:>2025-06-02.