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The stack pointer swap mechanism currently relies on the notion of levels to decide if a stack pointer swap is necessary.
This makes it rely on Smlic.
Also, this may lead to issues in double trap scenarios, or requires additional spec corner cases.
To make it more general, I propose the following:
The stack pointer register will have the low bits reserved as per the RISC-V calling convention. We can use the LSb to differentiate if the stack pointer belongs to regular execution or trap handling.
This way, upon entering the trap handler, the stack pointer can be swapped depending on whether the LSb of the xsp register has the LSb asserted or not. This also simplifies the overall logic, and arguably eases DV.
The text was updated successfully, but these errors were encountered:
The stack pointer swap mechanism currently relies on the notion of levels to decide if a stack pointer swap is necessary.
This makes it rely on Smlic.
Also, this may lead to issues in double trap scenarios, or requires additional spec corner cases.
To make it more general, I propose the following:
The stack pointer register will have the low bits reserved as per the RISC-V calling convention. We can use the LSb to differentiate if the stack pointer belongs to regular execution or trap handling.
This way, upon entering the trap handler, the stack pointer can be swapped depending on whether the LSb of the xsp register has the LSb asserted or not. This also simplifies the overall logic, and arguably eases DV.
The text was updated successfully, but these errors were encountered: