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Issues: riscv/riscv-zilsd
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Atomic LD writeback requirement is expensive for small cores
public review
Issues received during public review
#51
opened Oct 19, 2024 by
Wren6991
Unclarity about whether load/store pair are interruptible or not
public review
Issues received during public review
#46
opened Sep 19, 2024 by
Silabs-ArjanB
Include a register pair -> register pair move instruction
#15
opened May 23, 2024 by
anderslindgren-iar
Register pair instructions should use a
(rx, ry)
syntax
#14
opened May 23, 2024 by
anderslindgren-iar
ProTip!
Updated in the last three days: updated:>2024-11-05.