Fix delegated interrupt handling #613
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When the N extension was removed this code was accidentally broken because it doesn't respect mie for delegated interrupts any more. The `internal_error`s should be unreachable, at least for the sequential output. I believe formal backends may decide `mideleg` is going to be non-zero even without S, but I think that was an existing issue.
| Ints_Delegated(d) => { | ||
| if not(extensionEnabled(Ext_S)) then { | ||
| // Can't delegate to user mode. This code is unreachable because | ||
| // `mideleg.bits` is 0 without supervisor mode. |
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Well, the CSR doesn't exist so can't be written to by software and thus the Sail register remains its initial 0 value. The comment written here suggests that the CSR exists and is hardwired to 0 (which was the case in early specs).
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The Sail register mideleg always exists. That's what I was referring to. Not sure how to make that clearer...
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@KotorinMinami does this look right to you? |
So I think we might need to reflect this in the implementation of the sail's mideleg register, maybe this is the way to solve delegated interrupt handling? Moreover, based on what is said in spec, we can handle whether medeleg and mideleg exist and the delegated issues by checking misa
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This is handled by |
When the N extension was removed this code was accidentally broken because it doesn't respect mie for delegated interrupts any more.
The
internal_errors should be unreachable, at least for the sequential output. I believe formal backends may decidemidelegis going to be non-zero even without S, but I think that was an existing issue.