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Hypervisor Implementation Status
This page is meant to track progress, TODOs, and issues for the Hypervisor extensions implementation. The goal is to coordinate the work for adding Hypervisor support to the Sail RISC-V Model and to provide contributors a clear overview of ongoing progress, open tasks, and known issues.
Due to the complexity and intrusive nature of the hypervisor extension, many extensions interact with the hypervisor extension in one way or another and need to be reviewed. In particular, beyond adding the hypervisor-only components, extensions may need to:
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be slightly modified to handle additional complexity and functionality (e.g. Smstateen, Sdext, etc.) , or
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remain unmodified, with the hypervisor instead adding control mechanisms that allow or restrict access (e.g. Vector and Floating-Point).
The following tables list the extensions that need to be reviewed.
| Extension | Status | Developer | PR/Issue |
|---|---|---|---|
| F | |||
| V | |||
| Zicbom | |||
| Zicboz | |||
| Zicfilp | |||
| Zicfiss |
| Extension | Status | Developer | PR/Issue |
|---|---|---|---|
| Smstateen/Ssstateen | |||
| Smcsrind/Sscsrind | |||
| Smcdeleg/Ssccfg | |||
| Smctr | |||
| Svinval | |||
| Svrsw60t59b | |||
| Sstc | |||
| Ssdbltrp | |||
| Ssnpm/Smnpm | |||
| Smcntrpmf | |||
| Svadu | |||
| Sscofpmf | |||
| Shlcofideleg |
| Extension | Status | Developer | PR/Issue |
|---|---|---|---|
| Sdext | |||
| Sdtrig |
| Extension | Status | Developer | PR/Issue |
|---|---|---|---|
| Smaia/Ssaia |
Besides revising existing extensions, the Hypervisor extension introduces a significant amount of new code that needs to be implemented. This includes granular CSR access handling, two-stage address translation, virtualization of exceptions and timers, support for new instructions, and more.
A draft PR for the Hypervisor extension has already been opened by defermelowie. It can serve as a starting point for follow-up PRs, whether contributors want to extract smaller pieces or build on top of the existing work: https://github.com/riscv/sail-riscv/pull/612
The tables below list tasks with their current status, TODOs, and known issues for contributors to reference.
Note: The table is a work in progress and will continue to evolve. It is not yet complete and will be expanded as additional tasks, TODOs, and issues are identified.
| Title | Status | Developer | PR |
|---|---|---|---|
| Add Hypervisor Extension | Draft PR | trdthg | 1419 |
| Add csr_name_map and is_CSR_defined for H_ext registers | PR in Review | trdthg | 1110 |
| Add H_ext trap_handler support | PR in Review | KotorinMinami | 1290 |
| Title | Note |
|---|---|
| Add two-stage address translation | |
| Add Hypervisor Instructions | |
| Adapt system instructions (ECALL, SRET, WFI, SFENCE_VMA) | See base_insts.sail |
| Augment and modify machine CSRs (mstatus, mstatush, mideleg, mip, and mie, and add CSRs mtval2 and mtinst) | |
| Handle hart reset appropriately (set hgatp.MODE and vsatp.MODE to 0) |
| Title | Developer | Issue |
|---|---|---|
| How about having is_CSR_accessible return enum? | trdthg | 1350 |