Update value of misa

robotman2412 · Dec 30, 2023 · 0326bd9 · 0326bd9
1 parent f343754
commit 0326bd9
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Showing 2 changed files with 19 additions and 6 deletions.
diff --git a/README.md b/README.md
@@ -24,15 +24,15 @@ With the following CSRs present, all mandatory:
 | CSR address | CSR name     | Default value | Features
 | :---------- | :----------- | :------------ | :-------
 | `0x300`     | `mstatus`    | `0x0000_0000` | MIE and MPIE bits
-| `0x301`     | `misa`       | `0x4001_0100` | Read-only query of ISA
+| `0x301`     | `misa`       | `0x4000_1104` | Read-only query of ISA (RV32IMC)
 | `0x302`     | `medeleg`    | `0x0000_0000` | (unimplemented)
 | `0x303`     | `mideleg`    | `0x0000_0000` | (unimplemented)
 | `0x304`     | `mie`        | `0x0000_0000` | Read/write any interrupt enable
 | `0x305`     | `mtvec`      | `0x0000_0000` | Read/write direct exception vector
 | `0x310`     | `mstatush`   | `0x0000_0000` | (unimplemented)
 | `0x344`     | `mip`        | `0x0000_0000` | Read-only query of pending interrupts
 | `0x340`     | `mscratch`   | `0x0000_0000` | Read/write any value
-| `0x341`     | `mepc`       | `0x0000_0000` | Read/write any legal address
+| `0x341`     | `mepc`       | `0x0000_0000` | Read/write any legal PC
 | `0x342`     | `mcause`     | `0x0000_0000` | WARL trap and exception cause
 | `0x343`     | `mtval`      | `0x0000_0000` | (unimplemented)
 | `0xf11`     | `mvendorid`  | `0x0000_0000` | (unimplemented)

diff --git a/hdl/boa32_cpu.sv b/hdl/boa32_cpu.sv
@@ -144,7 +144,7 @@ module boa32_cpu#(
     /* ==== CSR logic ==== */
     boa_csr_bus csr();
     boa_csr_ex_bus csr_ex();
-    boa32_csrs#(.hartid(hartid)) csrs(clk, rst, csr, csr_ex);
+    boa32_csrs#(.hartid(hartid), .has_c(has_c)) csrs(clk, rst, csr, csr_ex);
 
 
     /* ==== Control transfer logic ==== */
@@ -515,7 +515,11 @@ endmodule
 // Boa³² CSR register file.
 module boa32_csrs#(
     // CSR mhartid value.
-    parameter hartid        = 32'h0000_0000
+    parameter hartid        = 32'h0000_0000,
+    // Support RVC instructions.
+    parameter has_c         = 1,
+    // Support RVM instructions.
+    parameter has_m         = 1
 )(
     // CPU clock.
     input  logic        clk,
@@ -540,7 +544,16 @@ module boa32_csrs#(
     // CSR mstatus: M-mode status.
     wire [31:0] csr_mstatus     = (csr_mstatus_mie << 3) | (csr_mstatus_mpie << 7);
     // CSR misa: M-mode ISA description.
-    wire [31:0] csr_misa        = 32'h4001_0100;
+    wire [31:0] csr_misa;
+    assign csr_misa[1:0]   = 0;
+    assign csr_misa[2]     = has_c;
+    assign csr_misa[7:3]   = 0;
+    assign csr_misa[8]     = 1;
+    assign csr_misa[11:9]  = 0;
+    assign csr_misa[12]    = has_m;
+    assign csr_misa[25:13] = 0;
+    assign csr_misa[29:26] = 0;
+    assign csr_misa[31:30] = 2'b01;
     // CSR medeleg: M-mode trap delegation.
     wire [31:0] csr_medeleg     = 0;
     // CSR medeleg: M-mode interrupt delegation.
@@ -564,7 +577,7 @@ module boa32_csrs#(
     // CSR mvendorid: M-mode vendor ID.
     wire [31:0] csr_mvendorid   = 0;
     // CSR mvendorid: M-mode architecture ID.
-    wire [31:0] csr_marchid     = 0;
+    wire [31:0] csr_marchid     = 34;
     // CSR mvendorid: M-mode implementation ID.
     wire [31:0] csr_mipid       = 0;
     // CSR mvendorid: M-mode implementation ID.