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ccu: move factor judgement into ccu module, add divide submodule
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reformat code

Signed-off-by: Zhouqi Jiang <[email protected]>
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luojia65 committed Nov 8, 2024
1 parent 75c03a3 commit 75fd1a8
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Showing 4 changed files with 60 additions and 50 deletions.
29 changes: 5 additions & 24 deletions allwinner-hal/src/ccu.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,10 @@
//! Clock Control Unit peripheral.
mod divide;

pub(crate) use divide::calculate_best_factors_nm;
pub use divide::{FactorN, FactorP};

use crate::ccu;
use embedded_time::rate::Hertz;
use volatile_register::RW;
Expand Down Expand Up @@ -625,30 +630,6 @@ impl DramBusGating {
}
}

/// Clock divide factor N.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum FactorN {
/// Don't divide.
N1,
/// Divide frequency by 2.
N2,
/// Divide frequency by 4.
N4,
/// Divide frequency by 8.
N8,
}

/// Clock divide factor P.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum FactorP {
/// Don't divide.
P1,
/// Divide frequency by 2.
P2,
/// Divide frequency by 4.
P4,
}

/// UART Bus Gating Reset register.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
#[repr(transparent)]
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50 changes: 50 additions & 0 deletions allwinner-hal/src/ccu/divide.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
/// Clock divide factor N.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum FactorN {
/// Don't divide.
N1,
/// Divide frequency by 2.
N2,
/// Divide frequency by 4.
N4,
/// Divide frequency by 8.
N8,
}

/// Clock divide factor P.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum FactorP {
/// Don't divide.
P1,
/// Divide frequency by 2.
P2,
/// Divide frequency by 4.
P4,
}

/// Calculate the best N-M divide factors from `f_src` and `f_dst` parameters.
#[inline]
pub fn calculate_best_factors_nm(f_src: u32, f_dst: u32) -> (FactorN, u8) {
let mut err = f_src;
let (mut best_n, mut best_m) = (0, 0);
for m in 1u8..=16 {
for n in [1, 2, 4, 8] {
let actual = f_src / n / m as u32;
if actual.abs_diff(f_dst) < err {
err = actual.abs_diff(f_dst);
(best_n, best_m) = (n, m);
}
}
}
let factor_n = match best_n {
1 => FactorN::N1,
2 => FactorN::N2,
4 => FactorN::N4,
8 => FactorN::N8,
_ => unreachable!(),
};
let factor_m = best_m - 1;
(factor_n, factor_m)
}

// TODO: test module
27 changes: 3 additions & 24 deletions allwinner-hal/src/spi.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
//! Serial Peripheral Interface bus.
use crate::ccu::{self, ClockConfig, ClockGate, Clocks, FactorN, SpiClockSource};
use crate::ccu::{self, ClockConfig, ClockGate, Clocks, SpiClockSource};
use core::cell::UnsafeCell;
use embedded_hal::spi::Mode;
use embedded_time::rate::Hertz;
Expand Down Expand Up @@ -303,29 +303,8 @@ impl<SPI: AsRef<RegisterBlock>, const I: usize, PINS: Pins<I>> Spi<SPI, I, PINS>
ccu: &ccu::RegisterBlock,
) -> Self {
// 1. unwrap parameters
let (Hertz(freq), Hertz(psi)) = (freq, clocks.psi);
let (factor_n, factor_m) = {
let mut err = psi;
let (mut best_n, mut best_m) = (0, 0);
for m in 1u8..=16 {
for n in [1, 2, 4, 8] {
let actual = psi / n / m as u32;
if actual.abs_diff(freq) < err {
err = actual.abs_diff(freq);
(best_n, best_m) = (n, m);
}
}
}
let factor_n = match best_n {
1 => FactorN::N1,
2 => FactorN::N2,
4 => FactorN::N4,
8 => FactorN::N8,
_ => unreachable!(),
};
let factor_m = best_m - 1;
(factor_n, factor_m)
};
let (Hertz(psi), Hertz(freq)) = (clocks.psi, freq);
let (factor_n, factor_m) = ccu::calculate_best_factors_nm(psi, freq);
// 2. init peripheral clocks
// Reset and reconfigure clock source and divider
unsafe { PINS::Clock::reconfigure(ccu, SpiClockSource::PllPeri1x, factor_m, factor_n) };
Expand Down
4 changes: 2 additions & 2 deletions rfel/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ fn main() {
Commands::Version => {
let version = fel.get_version();
println!("{:x?}", version);
},
}
Commands::Hexdump { address, length } => {
let address: usize = match parse_value(address.trim()) {
Some(address) => address,
Expand Down Expand Up @@ -122,7 +122,7 @@ fn main() {
}
};
fel.write_address(address, &value.to_le_bytes());
},
}
}
}

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