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  • Austin, Texas

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shanehnguyen/README.md

Welcome 👋

If you’re new here, start with these:

🧠 CPU

➡️ Pipelined RISC CPU (Verilog)

  • 5-stage pipeline
  • Data forwarding, load-use stalling, branch flush
  • Built + debugged at the cycle level

🧩 Cache

➡️ MESI Cache Coherence Simulator

  • Multi-core, bus-based coherence
  • Handles races, invalidations, writebacks
  • Stress-tested beyond “happy path” cases

I work mostly on computer architecture, embedded systems, and hardware-adjacent software.

Pinned Loading

  1. Cache-Coherence-Simulator Cache-Coherence-Simulator Public

    Cycle-accurate, multi-core cache coherence simulator that implements MESI protocol

    C++ 1

  2. RISC-CPU-Simulator RISC-CPU-Simulator Public

    Cycle-accurate LC-3 CPU simulator modeling pipelined execution, hazards, forwarding, and interrupt handling, with performance instrumentation

    Verilog

  3. Barbell-Velocity-Tracking-Clip-Front-End Barbell-Velocity-Tracking-Clip-Front-End Public

    Front-end application for visualizing real-time barbell velocity and acceleration data streamed from an ESP32-based embedded device.

    JavaScript

  4. Barbell-Velocity-Tracking-Clip-Back-End Barbell-Velocity-Tracking-Clip-Back-End Public

    Backend service for ingesting, processing, and storing barbell velocity and acceleration data streamed from an ESP32-based embedded device.

    C

  5. Character-Bigram-Language-Model Character-Bigram-Language-Model Public

    Character-level bigram model for generating names based on empirical bigram probabilities.

    Python 2