feature/starfive regmaps

README.md

@@ -1,2 +1,22 @@
 # cmsis-svd-generator
 Generates CMSIS-SVD xml files from DTS info and Register templates in the regmaps directory.
+
+# Generating a compatible DTS file
+
+Many DTS files are multi-level, and have both C and DSTI includes.
+
+To flatten the DTS file, one can run the C preprocessor and device tree compiler:
+
+```bash
+# run CPP to handle any C-style includes
+
+cpp -nostdinc -I include -I arch  -undef -x assembler-with-cpp /path/to/input.dts > processed.dts
+
+# run DTC to handle any DTSI includes
+
+dtc -I dts -O dts -o output.dts processed.dts
+
+# finally, run generate-svd.py
+
+./generate-svd.py -o output.svd -d output.dts
+```

generate_svd.py

@@ -7,13 +7,31 @@
 """
 
 import argparse
+import logging
 import os
 import sys
 import inspect
 import pydevicetree
+from scripts.arm_pl022 import generate_registers_arm_pl022
+from scripts.cdns_qspi_nor import generate_registers_cdns_qspi
 from scripts.riscv_clint0_control import generate_registers_riscv_clint0
 from scripts.sifive_clic0_control import generate_registers_sifive_clic0
 from scripts.riscv_plic0_control import generate_registers_riscv_plic0
+from scripts.snps_designware_i2c import generate_registers_snps_designware_i2c
+from scripts.snps_dw_apb_uart import generate_registers_snps_dw_apb_uart
+from scripts.starfive_common import generate_interrupt
+from scripts.starfive_jh7110_dmc_ctrl import generate_registers_starfive_jh7110_dmc_ctrl
+from scripts.starfive_jh7110_dmc_phy import generate_registers_starfive_jh7110_dmc_phy
+from scripts.starfive_jh7110_pmu import generate_registers_starfive_jh7110_pmu
+from scripts.starfive_jh7110_stgcrg import generate_registers_starfive_jh7110_stgcrg
+from scripts.starfive_jh7110_syscrg import generate_registers_starfive_jh7110_syscrg
+from scripts.starfive_jh7110_aoncrg import generate_registers_starfive_jh7110_aoncrg
+from scripts.starfive_jh7110_aon_pinctrl import generate_registers_starfive_jh7110_aon_iomux_cfg
+from scripts.starfive_jh7110_aon_syscon import generate_registers_starfive_jh7110_aon_syscon
+from scripts.starfive_jh7110_stg_syscon import generate_registers_starfive_jh7110_stg_syscon
+from scripts.starfive_jh7110_sys_pinctrl import generate_registers_starfive_jh7110_sys_iomux_cfg
+from scripts.starfive_jh7110_sys_syscon import generate_registers_starfive_jh7110_sys_syscon
+from scripts.starfive_jh7110_trng import generate_registers_starfive_jh7110_trng
 
 def parse_arguments(argv):
     """Parse the arguments into a dictionary with argparse"""
@@ -24,6 +42,10 @@ def parse_arguments(argv):
     arg_parser.add_argument("-o", "--output", required=True,
                             type=argparse.FileType('w'),
                             help="The path of the CMSIS SVD file to output")
+    arg_parser.add_argument("-l", "--log", required=False,
+                            default="WARN",
+                            type=str,
+                            help="The path of the CMSIS SVD file to output")
 
     return arg_parser.parse_args(argv)
 
@@ -63,58 +85,204 @@ def generate_peripherals(dts):
                 idx[compatible] = 0
 
     for peripheral in soc.child_nodes():
-        if peripheral.get_field("compatible") is not None and \
-            peripheral.get_field("reg-names") is not None:
+        if peripheral.get_field("compatible") is not None:
+            reg = peripheral.get_fields("reg")
+
+            if reg is None:
+                reg_cells = 0
+            else:
+                reg_cells = len(peripheral.get_fields("reg").values)
+
+            exp_reg_cells = peripheral.address_cells() + peripheral.size_cells()
+
+            if peripheral.get_fields("reg") is not None and reg_cells % exp_reg_cells != 0:
+                logging.debug("Unexpected number of reg cells {}, expected {}".format(reg_cells, exp_reg_cells)) 
+                continue
+
             compatibles = peripheral.get_fields("compatible")
-            reg_names = peripheral.get_fields("reg-names")
+
+            reg_names = {}
+            if peripheral.get_field("reg-names") is not None:
+                reg_names = peripheral.get_fields("reg-names")
+            else:
+                reg_names = {""}
+
             for comp in compatibles:
                 for reg in reg_names:
+                    if len(reg) == 0:
+                        rn = ""
+                    else:
+                        rn = "_" + reg
+
                     regmap_root = os.path.abspath(os.path.dirname(sys.argv[0]))
-                    regmap_name = get_name_as_id(comp) + "_" + reg + ".svd"
+                    regmap_name = get_name_as_id(comp) + rn + ".svd"
                     regmap_path = os.path.join(regmap_root, "regmaps", regmap_name)
-                    script_name = get_name_as_id(comp) + "_" + reg + ".py"
+                    script_name = get_name_as_id(comp) + rn + ".py"
                     script_path = os.path.join(regmap_root, "scripts", script_name)
+
+                    logging.debug("Compatible: {}".format(comp))
+                    logging.debug("    Regmap path: {}".format(regmap_path))
+                    logging.debug("    Script path: {}".format(script_path))
+
+                    if "clint" in comp and not os.path.exists(script_path):
+                        regmap_path = ""
+                        script_path = os.path.join(regmap_root, "scripts", "riscv_clint0_control.py")
+                    elif "plic" in comp and not os.path.exists(script_path):
+                        regmap_path = ""
+                        script_path = os.path.join(regmap_root, "scripts", "riscv_plic0_control.py")
+                    elif "clic" in comp and not os.path.exists(script_path):
+                        regmap_path = ""
+                        script_path = os.path.join(regmap_root, "scripts", "sifive_clic0_control.py")
+
                     if os.path.exists(regmap_path):
                         ext = str(idx[comp])
+                        logging.info("Regmap path: {}".format(regmap_path))
                         txt += generate_peripheral(dts, peripheral, comp, ext, reg, regmap_path)
                         idx[comp] += 1
                     elif os.path.exists(script_path):
                         ext = str(idx[comp])
+                        logging.info("Script path: {}".format(script_path))
                         txt += generate_peripheral(dts, peripheral, comp, ext, reg, script_path)
                         idx[comp] += 1
+                    else:
+                        ext = str(idx[comp])
+                        txt += generate_peripheral(dts, peripheral, comp, ext, reg, "")
+                        idx[comp] += 1
 
     return txt
 
 #pylint: disable=too-many-arguments
 def generate_peripheral(dts, peripheral, comp, ext, reg, regmap_path):
     """Generate xml string for peripheral"""
     reg_dict = peripheral.get_reg()
+
+    if reg_dict is None:
+        logging.debug("No peripheral found for {}".format(peripheral))
+        return ""
+
     reg_pair = reg_dict.get_by_name(reg)
+
+    addr_cells = peripheral.address_cells()
+    size_cells = peripheral.size_cells()
+    group_size = addr_cells + size_cells
+
+    if reg_pair is None and len(reg_dict.values) == group_size:
+        # no reg-names field was present, so parse according to the spec
+        reg_pair = [reg_dict.values[addr_cells - 1], reg_dict.values[group_size - 1]]
+    elif reg_pair is None:
+        logging.debug("Malformed DTS entry: {}".format(peripheral))
+        # malformed DTS, give up
+        return ""
+
     reg_desc = comp + """,""" + reg
-    print("Emitting registers for '" + peripheral.name + "' soc peripheral node")
+    logging.info("Emitting registers for '" + peripheral.name + "' soc peripheral node")
+
+    if regmap_path.endswith("arm_pl022.py"):
+        name = "spi{}".format(ext)
+    elif regmap_path.endswith("cdns_qspi_nor.py"):
+        name = "qspi".format(ext)
+    elif regmap_path.endswith("riscv_clint0_control.py"):
+        name = "clint"
+    elif regmap_path.endswith("riscv_plic0_control.py"):
+        name = "plic"
+    elif regmap_path.endswith("sifive_clic0_control.py"):
+        name = "clic"
+    elif regmap_path.endswith("snps_dw_apb_uart.py"):
+        name = "uart{}".format(ext)
+    elif regmap_path.endswith("snps_designware_i2c.py"):
+        name = "i2c{}".format(ext)
+    elif regmap_path.endswith("starfive_jh7110_pmu.py"):
+        name = "pmu"
+    elif regmap_path.endswith("starfive_jh7110_syscrg.py"):
+        name = "syscrg"
+    elif regmap_path.endswith("starfive_jh7110_stgcrg.py"):
+        name = "stgcrg"
+    elif regmap_path.endswith("starfive_jh7110_aoncrg.py"):
+        name = "aoncrg"
+    elif regmap_path.endswith("starfive_jh7110_aon_pinctrl.py"):
+        name = "aon_pinctrl"
+    elif regmap_path.endswith("starfive_jh7110_aon_syscon.py"):
+        name = "aon_syscon"
+    elif regmap_path.endswith("starfive_jh7110_stg_syscon.py"):
+        name = "stg_syscon"
+    elif regmap_path.endswith("starfive_jh7110_sys_pinctrl.py"):
+        name = "sys_pinctrl"
+    elif regmap_path.endswith("starfive_jh7110_sys_syscon.py"):
+        name = "sys_syscon"
+    elif regmap_path.endswith("starfive_jh7110_pwm.py") or regmap_path.endswith("starfive_jh7110_pwm.svd"):
+        name = "pwm"
+    elif regmap_path.endswith("starfive_jh7110_trng.py"):
+        name = "trng"
+    elif regmap_path.endswith("starfive_jh7110_dmc_ctrl.py"):
+        name = "dmc_ctrl"
+    elif regmap_path.endswith("starfive_jh7110_dmc_phy.py"):
+        name = "dmc_phy"
+    else:
+        name = "{}_{}".format(get_name_as_id(comp), ext)
 
     return """\
             <peripheral>
-              <name>""" + get_name_as_id(comp) + """_""" + ext + """</name>
+              <name>""" + name + """</name>
               <description>From """ + reg_desc + """ peripheral generator</description>
               <baseAddress>""" + "0x{:X}".format(reg_pair[0]) + """</baseAddress>
               <addressBlock>
                 <offset>0</offset>
                 <size>""" + "0x{:X}".format(reg_pair[1]) + """</size>
                 <usage>registers</usage>
               </addressBlock>
+""" + generate_interrupt("jh7110", name) + """\
 """ + generate_registers(dts, peripheral, regmap_path) + """\
             </peripheral>
 """
 
 def generate_registers(dts, peripheral, regmap_path):
+    if regmap_path == "":
+        logging.debug("No regmap file found for {}".format(peripheral))
+        logging.debug("\tRegmap path: {}".format(regmap_path))
+        # FIXME: instead of just giving up here, attempt to parse register data from the DTS
+        return ""
+
     """Generate xml string for registers from regmap file or generator code"""
+    if regmap_path.endswith("arm_pl022.py"):
+        return generate_registers_arm_pl022(dts, peripheral)
+    if regmap_path.endswith("cdns_qspi_nor.py"):
+        return generate_registers_cdns_qspi(dts, peripheral)
     if regmap_path.endswith("riscv_clint0_control.py"):
         return generate_registers_riscv_clint0(dts)
     if regmap_path.endswith("sifive_clic0_control.py"):
         return generate_registers_sifive_clic0(dts, peripheral)
     if regmap_path.endswith("riscv_plic0_control.py"):
         return generate_registers_riscv_plic0(dts, peripheral)
+    if regmap_path.endswith("snps_designware_i2c.py"):
+        return generate_registers_snps_designware_i2c(dts, peripheral)
+    if regmap_path.endswith("snps_dw_apb_uart.py"):
+        return generate_registers_snps_dw_apb_uart(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_dmc_ctrl.py"):
+        return generate_registers_starfive_jh7110_dmc_ctrl(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_dmc_phy.py"):
+        return generate_registers_starfive_jh7110_dmc_phy(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_pmu.py"):
+        return generate_registers_starfive_jh7110_pmu(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_syscrg.py"):
+        return generate_registers_starfive_jh7110_syscrg(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_stgcrg.py"):
+        return generate_registers_starfive_jh7110_stgcrg(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_aoncrg.py"):
+        return generate_registers_starfive_jh7110_aoncrg(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_aon_pinctrl.py"):
+        return generate_registers_starfive_jh7110_aon_iomux_cfg(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_aon_syscon.py"):
+        return generate_registers_starfive_jh7110_aon_syscon(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_stg_syscon.py"):
+        return generate_registers_starfive_jh7110_stg_syscon(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_sys_pinctrl.py"):
+        return generate_registers_starfive_jh7110_sys_iomux_cfg(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_sys_syscon.py"):
+        return generate_registers_starfive_jh7110_sys_syscon(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_trng.py"):
+        return generate_registers_starfive_jh7110_trng(dts, peripheral)
+
+    logging.debug("Reading registers from regmap file: {}".format(regmap_path))
 
     regmap_file = open(regmap_path, "r")
     txt = ""
@@ -128,7 +296,16 @@ def get_name_as_id(name):
 
 def main(argv):
     """Parse arguments, extract data, and render clean cmsis svd xml to file"""
+
+
     parsed_args = parse_arguments(argv)
+
+    # set the logging level from the command line
+    numeric_level = getattr(logging, parsed_args.log.upper(), None)
+    if not isinstance(numeric_level, int):
+        raise ValueError('Invalid log level: %s' % parsed_args.log)
+    logging.basicConfig(level=numeric_level)
+
     dts = pydevicetree.Devicetree.parseFile(parsed_args.dts, followIncludes=True)
     text = generate_device(dts)
     output = inspect.cleandoc(text)

regmaps/starfive_jh7110_pwm.svd

@@ -0,0 +1,102 @@
+<registers>
+  <register>
+    <name>cntr</name>
+    <description>PTC counter register</description>
+    <addressOffset>0x0</addressOffset>
+    <fields>
+      <field>
+        <name>cntr</name>
+        <description>PWM PTC counter</description>
+        <bitRange>[31:0]</bitRange>
+        <access>read-write</access>
+      </field>
+    </fields>
+  </register>
+  <register>
+    <name>hrc</name>
+    <description>PTC duty-cycle register</description>
+    <addressOffset>0x4</addressOffset>
+    <fields>
+      <field>
+        <name>hrc</name>
+        <description>PWM PTC duty-cycle value</description>
+        <bitRange>[31:0]</bitRange>
+        <access>read-write</access>
+      </field>
+    </fields>
+  </register>
+  <register>
+    <name>lrc</name>
+    <description>PTC period register</description>
+    <addressOffset>0x8</addressOffset>
+    <fields>
+      <field>
+        <name>lrc</name>
+        <description>PWM PTC period value</description>
+        <bitRange>[31:0]</bitRange>
+        <access>read-write</access>
+      </field>
+    </fields>
+  </register>
+  <register>
+    <name>ctrl</name>
+    <description>PTC control register</description>
+    <addressOffset>0xc</addressOffset>
+    <fields>
+      <field>
+        <name>en</name>
+        <description>PWM PTC enable</description>
+        <bitRange>[0:0]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>eclk</name>
+        <description>PWM PTC enable clock</description>
+        <bitRange>[1:1]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>nec</name>
+        <description>PWM PTC nec</description>
+        <bitRange>[2:2]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>oe</name>
+        <description>PWM PTC oe</description>
+        <bitRange>[3:3]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>single</name>
+        <description>PWM PTC single</description>
+        <bitRange>[4:4]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>inte</name>
+        <description>PWM PTC interrupt enable</description>
+        <bitRange>[5:5]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>int</name>
+        <description>PWM PTC interrupt</description>
+        <bitRange>[6:6]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>cntrrst</name>
+        <description>PWM PTC counter reset</description>
+        <bitRange>[7:7]</bitRange>
+        <access>read-write</access>
+      </field>
+      <field>
+        <name>capte</name>
+        <description>PWM PTC capte</description>
+        <bitRange>[8:8]</bitRange>
+        <access>read-write</access>
+      </field>
+    </fields>
+  </register>
+</registers>