tick-define macro substituted with incorrect value in json5

[ghost]

Following is verilog for which duh-import-verilog-ports incorrectly substitutes tick-define

`define IC_ADDR_SLICE_LHS 3'h7
module DW_apb_i2c (
                   paddr
                   );
   input [`IC_ADDR_SLICE_LHS:0] paddr; 
endmodule

the corresponding json5 generated is as follows

{
  component: {
    vendor: 'sifive',
    library: 'blocks',
    name: 'DW_apb_i2c',
    version: '0.1.0',
    busInterfaces: [],
    addressSpaces: [],
    memoryMaps: [],
    model: {
      views: [],
      ports: {
        $ref: '#/definitions/ports',
      },
    },
    fileSets: {},
    pSchema: {},
  },
  definitions: {
    ports: {
      paddr: '3 h7 + 1',
    },
  },
}

[drom]

Tick-define substitution was fine, but in the following expression

input [3'h7:0] paddr; 

The width of the signal was calculated as "3 h7 + 1"