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30 Open 36 Closed
30 Open 36 Closed
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Issues list

relax validation
#91 opened Oct 19, 2023 by mrwinsto
repetitive sets of items
#90 opened Sep 16, 2023 by drom
DuH validate not handling verbose port definitions
#87 opened Nov 10, 2020 by seldridge
DuH Validate Returns Zero Exit Code on Validation Failure
#86 opened Nov 9, 2020 by seldridge
1
Design option in "Block Type" doesn't create any (.json5) base document bug Something isn't working
#85 opened Nov 4, 2020 by adeelliaquat-lm
2
replace master/slave -> initiator/target
#79 opened Jul 2, 2020 by drom
1
think about linking programming interface to register description to bus interface
#76 opened Jun 8, 2020 by drom
detect type of the document
#75 opened Mar 26, 2020 by drom
warning about unmapped ports (component) enhancement New feature or request
#73 opened Mar 20, 2020 by drom
@drom
report status of DUH document
#67 opened Feb 13, 2020 by drom
10
Clarify README quickstart instructions regarding duh executable path
#64 opened Feb 3, 2020 by richardxia
cascading attributes: memoryMap -> register -> field
#63 opened Jan 30, 2020 by drom
duh validate doesn't find custom buses
#59 opened Nov 21, 2019 by olofk
2
CLIi to validate parameters against component parameter schema enhancement New feature or request
#57 opened Oct 2, 2019 by drom
Create a Python library for working with DUH?
#56 opened Sep 28, 2019 by mithro
4
duh-design
#55 opened Aug 21, 2019 by hiren-99
Import memory map of verilog to json5.
#52 opened Aug 21, 2019 by hiren-99
request for field to substitute different name for blackbox and block name
#50 opened Aug 20, 2019 by ghost
Can't map parts of signals in duh enhancement New feature or request
#40 opened May 7, 2019 by v-krvavac
@drom
Travis CI failing on Windows
#36 opened Apr 28, 2019 by drom
Travis CI failing on OSX
#35 opened Apr 28, 2019 by drom
@abishara
tick-define macro substituted with incorrect value in json5 bug Something isn't working
#33 opened Mar 25, 2019 by ghost
@Ramlakshmi3733
1
clean all unused references in the definition section
#27 opened Mar 7, 2019 by drom
1
Verilog integration export import
#16 opened Jan 26, 2019 by drom
2 of 4 tasks
SystemRDL integration export import registers
#15 opened Jan 25, 2019 by drom
1 task
ProTip! Exclude everything labeled bug with -label:bug.