Functional verification project for the CORE-V family of RISC-V cores. This project is under active development.
2020-09-04: a new (and much better) method of specifying and organizating test-programs and simulations is now merged in. See slide "Test Specification Updates" in the 2020-08-31 CV32E40P project update.
2020-06-12: a new "Board Support Package" for CV32E40P simulations is installed at cv32/bsp
. This BSP should be used to compile/assemble your test-programs. The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP.
2020-06-02: The Imperas OVPsim Instruction Set Generator has been integrated into the UVM environment as the Referenece Model for the CV32E40(P). You will need to obtain a license from Imperas to use it.
2020-02-28: The OpenHW Group CV32E40P is now live!
This repository no longer contains a local copy of the RTL. The RTL is cloned from the appropriate core-v-cores repository as needed. The specific branch and hash of the RTL is controlled by a set of variables in cv32/sim/Common.mk
.
First, have a look at the OpenHW Group's website to learn a bit more about who we are and what we are doing.
The design and verification documentation for the various CORE-V cores is located in the OpenHW Group's CORE-V documentation repo. Reading the Verification Strategy is strongly recommended.
If you want to run a simulation there are two options:
- To run the CORE testbench (based on the RI5CY testbench), go to
cv32/sim/core
and read the README. - To run the CV32E40P UVM environment, go to
cv32/sim/uvmt_cv32
and read the README.
To run CVA6 testbench, go to cva6 directory and read the README.
Various utilities for running tests and performing various verification-related activities in the core-v-verif repository.
Scriptware for user regression tests and an explainer for the Metrics continuous integration flow used by CORE-V-VERIF.
Empty sub-directory into which the RTL from one or more of the CORE-V-CORES repositories is cloned.
Verification Environments, testbenches, testcases and simulation Makefiles for the CV32E cores.
Verification Environments, testbenches, testcases and simulation Makefiles for the CVA6 cores.
Contains a pointer to the CORE-V-DOCS repository.
Common components for the CV32 and CVA6 verification environments.
Verification components supported by third-parties.
We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub
projects associated with this repository. Individual work-items
within a project are defined as issues with a task
label.
To ease our work of reviewing your contributions, please:
- Review CONTRIBUTING.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.