This repository contains an implementation of a simple priority encoder (code in SystemVerilog, reference model in Matlab).

The design was synthesized and implemented, followed by timing analysis (900 MHz frequency for _Zynq UltraScale+ RFSoCs (xczu48dr-fsvg1517-2-e)) and resource usage analysis (Figure 1 and 2, respectively).

The module test results for a bit depth of 5 (for clarity) are shown in Figure 3.

Fig.1. Timing analysis

Fig.2. Utilization report

Fig.3. TestBench result