TOOL CHECK

1. yosys
2. OpenSTA
3. ngspice
4. iverilog
5. gtkwave
6. magic

yosys:

installation:

$ git clone https://github.com/YosysHQ/yosys.git

//here I had created yosys directory in which github repo is cloned

$ cd yosys $ sudo apt-get install build-essential clang bison flex
libreadline-dev gawk tcl-dev libffi-dev git
graphviz xdot pkg-config python3 libboost-system-dev
libboost-python-dev libboost-filesystem-dev zlib1g-dev $ make $ sudo make install

Useful link: yosys

OpenSTA

installation:

$ git clone https://github.com/The-OpenROAD-Project/OpenSTA.git

$ cd OpenSTA

$ mkdir build

$ cd build

$ cmake ..

$ make

ngspice

installation:

$ sudo apt-get install ngspice

iverilog

installation:

$ sudo apt-get install iverilog

gtkwave

installation:

$ sudo apt-get install gtkwave

magic

installation:

$ sudo apt-get install m4

$ sudo apt-get install tcsh

$ sudo apt-get install csh

$ sudo apt-get install libx11-dev

$ sudo apt-get install tcl-dev tk-dev

$ sudo apt-get install libcairo2-dev

$ sudo apt-get install mesa-common-dev libglu1-mesa-dev

$ sudo apt-get install libncurses-dev

Simulator

executing steps:

• iverilog design_file.v testbench_design_file.v

// you can also give iverilog design_file.v testbench_design_file.v -o design_executable

• ./a.out

//this a.out executable file is generated or ./design_executable if you have specified any

• testbench_design_file.vcd

//vcd dump file is generated

• gtkwave testbench_design_file.vcd

//waveform viewer will openup with the input & output stimulus.

synthesis

executing steps:

1. read_liberty -lib $PATH/*.lib

// in our case read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

• you are reading the .lib content //all the models

2. read_verilog design.v

//reading the design or loading the design

3. synth -top design_name

//give design_name for it to be relevant

• read the statistics it prints to see the models it loads for the design.

4. abc -liberty $PATH/*.lib

//technology mapping using ABC

5. show design_name

//design_name given in the synthesis run step.3 "synth -top design_name"

6. write_verilog -noattr design_name_netlist.v

//writing out the synthesized netlist with technology mapped logic gates

GLS [Gate Level Simulation]

link: https://github.com/snallaga9/VSD-HDP-digital/wiki/WEEK-1#day-4--gls-gate-level-simulation