Merge pull request #17 from stnolting/dependabot/submodules/neorv32-8…

…7a78de [Dependabot]: Bump neorv32 from `01e88db` to `87a78de`
stnolting · Jan 19, 2025 · 017e689 · 017e689
2 parents e8e3d1b + efb86c9
commit 017e689
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Showing 2 changed files with 3 additions and 7 deletions.
diff --git a/neorv32 b/neorv32
diff --git a/sim/neorv32_vuinit_tb.vhd b/sim/neorv32_vuinit_tb.vhd
@@ -75,7 +75,7 @@ architecture neorv32_vunit_tb_rtl of neorv32_vunit_tb is
   signal uart0_cts, uart1_cts : std_ulogic;
 
   -- gpio --
-  signal gpio : std_ulogic_vector(63 downto 0);
+  signal gpio : std_ulogic_vector(31 downto 0);
 
   -- twi --
   signal i2c_scl, i2c_sda : std_logic;
@@ -256,10 +256,8 @@ begin
     XIP_CACHE_EN          => true,
     XIP_CACHE_NUM_BLOCKS  => 4,
     XIP_CACHE_BLOCK_SIZE  => 256,
-    -- External Interrupts Controller (XIRQ) --
-    XIRQ_NUM_CH           => 32,
     -- Processor peripherals --
-    IO_GPIO_NUM           => 64,
+    IO_GPIO_NUM           => 32,
     IO_CLINT_EN           => true,
     IO_UART0_EN           => true,
     IO_UART0_RX_FIFO      => 32,
@@ -375,8 +373,6 @@ begin
     neoled_o       => open,
     -- Machine timer system time (available if IO_MTIME_EN = true) --
     mtime_time_o   => open,
-    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
-    xirq_i         => gpio(31 downto 0),
     -- CPU Interrupts --
     mtime_irq_i    => '0',
     msw_irq_i      => msi_ring,
+4 −5		.github/workflows/Processor.yml
+5 −1		CHANGELOG.md
+1 −3		README.md
+9 −0		docs/datasheet/on_chip_debugger.adoc
+1 −2		docs/datasheet/overview.adoc
+7 −12		docs/datasheet/soc.adoc
+58 −18		docs/datasheet/soc_gpio.adoc
+1 −1		docs/datasheet/soc_sysinfo.adoc
+20 −16		docs/datasheet/soc_twd.adoc
+9 −1		docs/datasheet/soc_wdt.adoc
+5 −0		docs/datasheet/soc_xbus.adoc
+0 −82		docs/datasheet/soc_xirq.adoc
+0 −1		docs/datasheet/software.adoc
+ −		docs/figures/neorv32_processor.png
+1 −3		docs/userguide/adding_custom_hw_modules.adoc
+1 −1		docs/userguide/application_specific_configuration.adoc
+12 −15		rtl/core/neorv32_application_image.vhd
+130 −131		rtl/core/neorv32_bootloader_image.vhd
+4 −3		rtl/core/neorv32_bus.vhd
+1 −7		rtl/core/neorv32_cache.vhd
+1 −1		rtl/core/neorv32_cpu_control.vhd
+89 −39		rtl/core/neorv32_gpio.vhd
+6 −8		rtl/core/neorv32_package.vhd
+26 −9		rtl/core/neorv32_sys.vhd
+2 −3		rtl/core/neorv32_sysinfo.vhd
+24 −52		rtl/core/neorv32_top.vhd
+13 −9		rtl/core/neorv32_twd.vhd
+68 −56		rtl/core/neorv32_xbus.vhd
+0 −201		rtl/core/neorv32_xirq.vhd
+0 −1		rtl/file_list_soc.f
+6 −6		rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
+5 −6		rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd
+44 −35		rtl/system_integration/neorv32_vivado_ip.tcl
+12 −24		rtl/system_integration/neorv32_vivado_ip.vhd
+17 −16		rtl/system_integration/xbus2axi4lite_bridge.vhd
+4 −6		sim/neorv32_tb.vhd
+2 −2		sw/bootloader/bootloader.c
+7 −4		sw/example/demo_clint/main.c
+3 −3		sw/example/demo_gpio/Makefile
+93 −0		sw/example/demo_gpio/main.c
+0 −184		sw/example/demo_xirq/main.c
+33 −40		sw/example/processor_check/main.c
+6 −9		sw/lib/include/neorv32.h
+26 −9		sw/lib/include/neorv32_gpio.h
+1 −1		sw/lib/include/neorv32_sysinfo.h
+3 −3		sw/lib/include/neorv32_twi.h
+0 −67		sw/lib/include/neorv32_xirq.h
+0 −1		sw/lib/source/neorv32_aux.c
+90 −39		sw/lib/source/neorv32_gpio.c
+10 −8		sw/lib/source/neorv32_rte.c
+0 −251		sw/lib/source/neorv32_xirq.c
+23 −52		sw/svd/neorv32.svd