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[Dependabot]: Bump neorv32 from `c78f082` to `06f3177`
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stnolting authored Nov 3, 2024
2 parents e6e91ca + a9a2b18 commit d78c422
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2 changes: 1 addition & 1 deletion neorv32
Submodule neorv32 updated 55 files
+27 −61 .github/workflows/Processor.yml
+3 −1 CHANGELOG.md
+3 −1 README.md
+1 −1 docs/datasheet/cpu_csr.adoc
+4 −4 docs/datasheet/overview.adoc
+62 −39 docs/datasheet/soc.adoc
+11 −15 docs/datasheet/soc_bootrom.adoc
+1 −1 docs/datasheet/soc_dmem.adoc
+20 −19 docs/datasheet/soc_imem.adoc
+33 −32 docs/datasheet/soc_sysinfo.adoc
+2 −2 docs/datasheet/software.adoc
+1 −1 docs/datasheet/software_bootloader.adoc
+ docs/figures/neorv32_boot_configurations.png
+8 −1 docs/userguide/packaging_vivado.adoc
+17 −96 docs/userguide/simulating_the_processor.adoc
+11 −6 rtl/core/neorv32_application_image.vhd
+14 −9 rtl/core/neorv32_bootloader_image.vhd
+1 −1 rtl/core/neorv32_bus.vhd
+1 −1 rtl/core/neorv32_cpu_control.vhd
+19 −19 rtl/core/neorv32_dmem.vhd
+31 −33 rtl/core/neorv32_imem.vhd
+6 −40 rtl/core/neorv32_package.vhd
+5 −2 rtl/core/neorv32_sysinfo.vhd
+46 −18 rtl/core/neorv32_top.vhd
+1 −1 rtl/core/neorv32_xbus.vhd
+0 −2 rtl/file_list_cpu.f
+2 −2 rtl/file_list_soc.f
+4 −3 rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
+4 −3 rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
+4 −3 rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd
+56 −29 rtl/system_integration/neorv32_vivado_ip.tcl
+26 −19 rtl/system_integration/neorv32_vivado_ip.vhd
+1 −1 rtl/system_integration/xbus2ahblite_bridge.vhd
+3 −2 rtl/test_setups/neorv32_test_setup_approm.vhd
+3 −2 rtl/test_setups/neorv32_test_setup_bootloader.vhd
+3 −2 rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd
+0 −24 sim/README.md
+2 −2 sim/ghdl.run.sh
+3 −3 sim/ghdl.setup.sh
+12 −0 sim/ghdl.sh
+216 −226 sim/neorv32_tb.vhd
+0 −56 sim/run.py
+0 −10 sim/simple/ghdl.sh
+0 −605 sim/simple/neorv32_tb.simple.vhd
+0 −77 sim/simple/uart_rx.simple.vhd
+11 −53 sim/uart_rx.vhd
+0 −60 sim/uart_rx_pkg.vhd
+15 −7 sw/common/common.mk
+1 −1 sw/example/hello_world/makefile
+1 −1 sw/example/processor_check/makefile
+45 −52 sw/image_gen/image_gen.c
+5 −2 sw/lib/include/neorv32_sysinfo.h
+16 −12 sw/lib/source/neorv32_rte.c
+2 −2 sw/lib/source/neorv32_uart.c
+5 −4 sw/svd/neorv32.svd
177 changes: 78 additions & 99 deletions sim/neorv32_vuinit_tb.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,6 @@ architecture neorv32_vunit_tb_rtl of neorv32_vunit_tb is
-- User Configuration ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- general --
constant int_imem_c : boolean := false; -- true: use proc-internal IMEM, false: use external simulated IMEM (ext. mem A)
constant int_dmem_c : boolean := false; -- true: use proc-internal DMEM, false: use external simulated DMEM (ext. mem B)
constant imem_size_c : natural := 32*1024; -- size in bytes of processor-internal IMEM / external mem A
constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
constant f_clock_c : natural := 100000000; -- main clock in Hz
Expand Down Expand Up @@ -191,12 +189,15 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_top_inst: neorv32_top
generic map (
-- General --
-- Processor Clocking --
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
CLOCK_GATING_EN => true, -- enable clock gating when in sleep mode
-- Identification --
HART_ID => x"00000000", -- hardware thread ID
JEDEC_ID => "00000000000", -- vendor's JEDEC ID
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- Boot Configuration --
BOOT_MODE_SELECT => 1, -- boot from custom boot address
BOOT_ADDR_CUSTOM => x"00000000", -- custom boot address
-- On-Chip Debugger (OCD) --
OCD_EN => true, -- implement on-chip debugger
OCD_AUTHENTICATION => true, -- implement on-chip debugger authentication
Expand Down Expand Up @@ -236,11 +237,9 @@ begin
HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_EN => false, -- no internal IMEM
-- Internal Data memory --
MEM_INT_DMEM_EN => int_dmem_c, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
MEM_INT_DMEM_EN => false, -- no internal DMEM
-- Internal Cache memory --
ICACHE_EN => false, -- implement instruction cache
-- Internal Data Cache (dCACHE) --
Expand Down Expand Up @@ -453,104 +452,84 @@ begin

-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
-- -------------------------------------------------------------------------------------------
generate_ext_imem:
if (int_imem_c = false) generate
ext_mem_a_access: process(clk_gen)
variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM
begin
if rising_edge(clk_gen) then
-- control --
ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge

-- write access --
if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
for i in 0 to 3 loop
if (wb_mem_a.sel(i) = '1') then
ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8);
end if;
end loop; -- i
end if;

-- read access --
ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
-- virtual read and ack latency --
if (ext_mem_a_latency_c > 1) then
for i in 1 to ext_mem_a_latency_c-1 loop
ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
end loop;
end if;

-- bus output register --
wb_mem_a.err <= '0';
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') then
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
wb_mem_a.ack <= '1';
else
wb_mem_a.rdata <= (others => '0');
wb_mem_a.ack <= '0';
end if;
ext_mem_a_access: process(clk_gen)
variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM
begin
if rising_edge(clk_gen) then
-- control --
ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge

-- write access --
if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
for i in 0 to 3 loop
if (wb_mem_a.sel(i) = '1') then
ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8);
end if;
end loop; -- i
end if;

-- read access --
ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
-- virtual read and ack latency --
if (ext_mem_a_latency_c > 1) then
for i in 1 to ext_mem_a_latency_c-1 loop
ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
end loop;
end if;
end process ext_mem_a_access;
end generate;

generate_ext_imem_false:
if (int_imem_c = true) generate
wb_mem_a.rdata <= (others => '0');
wb_mem_a.ack <= '0';
wb_mem_a.err <= '0';
end generate;
-- bus output register --
wb_mem_a.err <= '0';
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') then
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
wb_mem_a.ack <= '1';
else
wb_mem_a.rdata <= (others => '0');
wb_mem_a.ack <= '0';
end if;
end if;
end process ext_mem_a_access;


-- Wishbone Memory B (simulated external DMEM) --------------------------------------------
-- -------------------------------------------------------------------------------------------
generate_ext_dmem:
if (int_dmem_c = false) generate
ext_mem_b_access: process(clk_gen)
variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM
begin
if rising_edge(clk_gen) then
-- control --
ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge

-- write access --
if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
for i in 0 to 3 loop
if (wb_mem_b.sel(i) = '1') then
ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8);
end if;
end loop; -- i
end if;

-- read access --
ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
-- virtual read and ack latency --
if (ext_mem_b_latency_c > 1) then
for i in 1 to ext_mem_b_latency_c-1 loop
ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
end loop;
end if;

-- bus output register --
wb_mem_b.err <= '0';
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
wb_mem_b.ack <= '1';
else
wb_mem_b.rdata <= (others => '0');
wb_mem_b.ack <= '0';
end if;
ext_mem_b_access: process(clk_gen)
variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM
begin
if rising_edge(clk_gen) then
-- control --
ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge

-- write access --
if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
for i in 0 to 3 loop
if (wb_mem_b.sel(i) = '1') then
ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8);
end if;
end loop; -- i
end if;
end process ext_mem_b_access;
end generate;

generate_ext_dmem_false:
if (int_dmem_c = true) generate
wb_mem_b.rdata <= (others => '0');
wb_mem_b.ack <= '0';
wb_mem_b.err <= '0';
end generate;

-- read access --
ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
-- virtual read and ack latency --
if (ext_mem_b_latency_c > 1) then
for i in 1 to ext_mem_b_latency_c-1 loop
ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
end loop;
end if;

-- bus output register --
wb_mem_b.err <= '0';
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
wb_mem_b.ack <= '1';
else
wb_mem_b.rdata <= (others => '0');
wb_mem_b.ack <= '0';
end if;
end if;
end process ext_mem_b_access;


-- Wishbone Memory C (simulated external IO) ----------------------------------------------
Expand Down

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