Reduce number of BRAMs used for the ROMs

See Issue #39.

vhdl/block_rom.vhd

@@ -15,13 +15,13 @@ generic (
 port (
    clk         : in std_logic;                        -- read and write on rising clock edge
    ce          : in std_logic;                        -- chip enable, when low then zero on output
-   
+
    address     : in std_logic_vector(14 downto 0);    -- address is for now 15 bit hard coded
    data        : out std_logic_vector(ROM_WIDTH - 1 downto 0);   -- read data
-   
+
    -- 1=still executing, i.e. can drive CPU's WAIT_FOR_DATA, goes zero
    -- if not needed (ce = 0) and can therefore directly be connected to a bus
-   busy        : out std_logic                       
+   busy        : out std_logic
 );
 end BROM;
 
@@ -33,20 +33,34 @@ signal counter : std_logic := '1'; -- important to be initialized to one
 signal address_old : std_logic_vector(14 downto 0) := (others => 'U');
 signal async_reset : std_logic;
 
-type brom_t is array (0 to 2**address'length - 1) of bit_vector(ROM_WIDTH - 1 downto 0);
+impure function get_lines_in_romfile(rom_file_name : in string) return natural is
+   file     rom_file  : text is in rom_file_name;
+   variable line_v    : line;
+   variable lines_v   : natural := 0;
+begin
+   while not endfile(rom_file) loop
+      readline(rom_file, line_v);   -- Just ignore the line read from the file.
+      lines_v := lines_v + 1;
+   end loop;
+   return lines_v;
+end function;
+
+constant C_LINES : natural := get_lines_in_romfile(FILE_NAME);
+
+type brom_t is array (0 to C_LINES - 1) of bit_vector(ROM_WIDTH - 1 downto 0);
 
 impure function read_romfile(rom_file_name : in string) return brom_t is
-   file     rom_file  : text is in rom_file_name;                       
-   variable line_v    : line;                                 
+   file     rom_file  : text is in rom_file_name;
+   variable line_v    : line;
    variable rom_v     : brom_t;
-begin                                                        
-   for i in brom_t'range loop  
+begin
+   for i in brom_t'range loop
       if not endfile(rom_file) then
          readline(rom_file, line_v);
          read(line_v, rom_v(i));
       end if;
-   end loop;                                                    
-   return rom_v;                                                  
+   end loop;
+   return rom_v;
 end function;
 
 signal brom : brom_t := read_romfile(FILE_NAME);
@@ -56,17 +70,17 @@ begin
    -- process for read and write operation on the rising clock edge
    rom_read : process (clk)
    begin
-      if falling_edge(clk) then         
+      if falling_edge(clk) then
          if ce = '1' then
             output <= to_stdlogicvector(brom(conv_integer(address)));
          else
             output <= (others => 'U');
          end if;
-         
+
          address_old <= address;
       end if;
    end process;
-   
+
    -- zero while not ce
    manage_output : process (ce, output)
    begin
@@ -76,7 +90,7 @@ begin
          data <= output;
       end if;
    end process;
-   
+
    -- generate a busy signal for one clock cycle, because this is
    -- the read delay that this block RAM is having
    manage_busy : process (clk, async_reset)
@@ -108,7 +122,7 @@ begin
          async_reset <= '0';
       end if;      
    end process;
-
-   busy <= '0';
 
+   busy <= '0';
+
 end beh;