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Benchmarks
Details
| Benchmark suite | Current: 7554c3b | Previous: 584625f | Ratio |
|---|---|---|---|
Dhrystone |
1336 Average DMIPS over 10 runs |
1336 Average DMIPS over 10 runs |
1 |
Coremark |
948.638 Average iterations/sec over 10 runs |
957.189 Average iterations/sec over 10 runs |
1.01 |
This comment was automatically generated by workflow using github-action-benchmark.
howjmay
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How can you test the RVV instructions? |
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A test set own by chipsalliance is here. https://github.com/chipsalliance/riscv-vector-tests/tree/main I think we can test instructions' behavior with this repo. However, testing decoder is harder. I think I will Spike the verify the behavior, or generating the test cases |
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src/emulate.c
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| #include "rv32_template.c" | ||
| #if RV32_HAS(EXT_RVV) | ||
| #include "rv32_rvv_template.c" |
| /* | ||
| * This file is auto-generated by running 'make' in | ||
| * https://github.com/riscv/riscv-opcodes (9226b0d) | ||
| * and it is temporarily used by RVV only | ||
| */ |
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Related: #103
Do you think it makes sense to replace the existing hand-written RISC-V instruction decoder with the generated one?
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I think the current one is good for education, especially the comments are valuable.
However I think having a table to clearly store the instructions in human-readable form is good for the future development.
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But this encoding.h is only a temporary header file for me to decode rvv instructions.
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Close in favor of #545 |
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relate to #504