t-dasun

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Tharindu Dasun Pathirage t-dasun

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Working from home

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Senior Software Engineer with experience in embedded software development, C++, FPGA design, RISC-V architecture, and machine learning.

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t-dasun/README.md

👋 Hi, I’m Tharindu Dasun Pathirage, a Senior Software Engineer specializing in:

Embedded Systems (C++, FPGA, RISC-V, Verilog)
AI/ML Applications (Python, DNN, AI Chip Programming)
Cloud & DevOps (AWS, CI/CD, Linux Automation)
...

💡 Projects of Note:

🛠️ Multi-Prime RSA in Verilog (IEEE-published)
⚡ Hardware-Accelerated OpenSSL (FPGA-based AES/RSA optimizations)
🤖 AI Chip Simulators (C++11/14/17, Linux scripting)
...

📚 Certifications & Courses:

RISC-V Associate (Linux Foundation)
Machine Learning (Stanford/Coursera)
AWS Cloud Practitioner
...

🌟 Community:

IEEE Sri Lanka Section Leader (Membership Development, SWY Congress)
Mentor for System Verilog and C++ best practices

🔍 Looking to collaborate on open-source embedded systems, AI/ML, or FPGA projects.
📫 Let’s connect: LinkedIn | [email protected]

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AES AES Public

AES Verilog algo

Verilog 1
2LFSR_RNG512bit 2LFSR_RNG512bit Public

verilog

Verilog
RSA RSA Public

rsa/euclidean algorithm/primilty test

Verilog
Gemini-API-Cpp-class Gemini-API-Cpp-class Public

this application alow write C++ application with seprate headers and cpp . and also debug auto and regeneration part under development

Python
static-web static-web Public

SCSS
Thilina-Pathirage/bill_reader Thilina-Pathirage/bill_reader Public

Python