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+ `timescale 1ns / 1ps
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+
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+ module aes (
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+ input aclk, // Clock
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+ input aresetn, // Asynchronous reset active low
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+
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+ // encryption side
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+ input wire [127 : 0 ] key_enc,
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+ input wire key_init_enc,
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+ output wire key_ready_enc,
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+
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+ input wire [127 : 0 ] input_block_enc,
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+ output reg [127 : 0 ] output_block_enc,
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+ output reg block_ready_enc
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+
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+ // decryption side
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+ input wire [127 : 0 ] key_dec,
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+ input wire key_init_dec,
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+ output wire key_ready_dec,
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+
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+ input wire [127 : 0 ] input_block_dec,
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+ output reg [127 : 0 ] output_block_dec,
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+ output reg block_ready_dec
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+ );
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+ // ----------------------------------------------------------------
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+ // Parameters.
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+ // ----------------------------------------------------------------
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+
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+ // ---------------------------------------------------------------------------------------------------------------------
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+ // Internal wires and registers
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+ // ---------------------------------------------------------------------------------------------------------------------
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+
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+ // ----------------------------------------------------------------
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+ // assignments for ports.
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+ // ----------------------------------------------------------------
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+
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+ // ---------------------------------------------------------------------------------------------------------------------
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+ // Implementation
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+ // ---------------------------------------------------------------------------------------------------------------------
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+
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+ aes_encryption
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+ #(
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+ )aes_encryption_dut
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+ .aclk,
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+ .aresetn,
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+ .next,
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+ .keylen,
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+ .key,
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+ .key_init,
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+ .input_block,
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+ .output_block,
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+ .block_ready
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+ );
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+
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+ // ----------------------------------------------------------------
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+ // functions and sub functions.
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+
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+ endmodule // aes
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