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Add I2S module
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‎i2s/README.md

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### I2S Master
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Github: [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/i2s)
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This is a simple I2S master module written in Verilog.
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The module requires clock source which is used to derive MCLK and BCLK for the I2S interface.
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The audio_clk_i clock rate should be:
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* 32KHz - 16.384MHz
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* 44.1KHz - 22.5792MHz
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* 48KHz - 24.576MHz
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The frequency of clk_i must be more than 2 x audio_clk_i frequency.
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The input interface expects 32-bits (2 x 16-bit audio samples) to be provided to it on 'sample_i' and held until 'sample_req_o' is pulsed (data pop request).
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This allows connection to a simple FIFO for audio samples.
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##### Testing
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The supplied testbench requires the SystemC libraries and Icarus Verilog, both of which are available for free.

‎i2s/rtl/i2s.v

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//-----------------------------------------------------------------
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// I2S Master
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// V0.1
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// Ultra-Embedded.com
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// Copyright 2012
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//
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// Email: [email protected]
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//
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// License: GPL
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// If you would like a version with a more permissive license for
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// use in closed source commercial applications please contact me
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// for details.
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//-----------------------------------------------------------------
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//
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// This file is open source HDL; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// This file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this file; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//-----------------------------------------------------------------
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module i2s
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(
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// Main clock (min 2x audio_clk_i)
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input clk_i,
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input rst_i,
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// Audio clock (MCLK x 2):
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// For 44.1KHz: 22.5792MHz
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// For 48KHz: 24.576MHz
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input audio_clk_i,
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input audio_rst_i,
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// I2S DAC Interface
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output i2s_mclk_o,
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output i2s_bclk_o,
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output i2s_ws_o,
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output i2s_data_o,
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// Audio interface (16-bit x 2 = RL)
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// (synchronous to clk_i)
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input [31:0] sample_i,
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output sample_req_o
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);
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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reg [4:0] bit_count_q;
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// Registered audio input data
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reg [31:0] sample_q;
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// Xilinx: Place output flop in IOB
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//synthesis attribute IOB of mclk_q is "TRUE"
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//synthesis attribute IOB of ws_q is "TRUE"
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//synthesis attribute IOB of bclk_q is "TRUE"
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//synthesis attribute IOB of data_q is "TRUE"
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reg mclk_q;
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reg bclk_q;
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reg ws_q;
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reg data_q;
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reg sample_req_q;
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reg next_data_q;
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//-----------------------------------------------------------------
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// MCLK
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//-----------------------------------------------------------------
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reg [7:0] clock_div_q;
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always @(posedge audio_clk_i or posedge audio_rst_i)
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if (rst_i)
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begin
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mclk_q <= 1'b0;
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clock_div_q <= 8'b0;
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end
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else
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begin
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mclk_q <= !mclk_q;
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clock_div_q <= clock_div_q + 8'd1;
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end
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reg clk_en0_ms_q;
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reg clk_en1_q;
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reg clk_en2_q;
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// Resync clk enable pulse to clk_i domain
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always @(posedge clk_i or posedge rst_i)
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if (rst_i)
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begin
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clk_en0_ms_q <= 1'b0;
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clk_en1_q <= 1'b0;
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clk_en2_q <= 1'b0;
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end
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else
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begin
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clk_en0_ms_q <= (clock_div_q == 8'd0);
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clk_en1_q <= clk_en0_ms_q;
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clk_en2_q <= clk_en1_q;
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end
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// BCLK is div256 of MCLK
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wire bclk_en_w = !clk_en2_q && clk_en1_q;
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//-----------------------------------------------------------------
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// I2S Output Generator
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//-----------------------------------------------------------------
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always @(posedge clk_i or posedge rst_i)
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begin
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if (rst_i == 1'b1)
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begin
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sample_q <= 32'b0;
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bit_count_q <= 5'd0;
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data_q <= 1'b0;
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ws_q <= 1'b0;
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bclk_q <= 1'b0;
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next_data_q <= 1'b0;
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sample_req_q <= 1'b0;
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end
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else if (bclk_en_w)
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begin
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// BCLK 1->0 - Falling Edge
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if (bclk_q)
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begin
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bclk_q <= 1'b0;
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data_q <= next_data_q;
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next_data_q <= sample_q[5'd31 - bit_count_q];
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// Word select
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ws_q <= bit_count_q[4];
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// Increment bit position counter
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bit_count_q <= bit_count_q + 5'd1;
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end
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// BCLK 0->1 - Rising Edge
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else
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begin
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bclk_q <= 1'b1;
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// Last bit in first half, buffer remainder and pop word
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if (bit_count_q == 5'd0)
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begin
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sample_q <= {sample_i[15:0], sample_i[31:16]};
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sample_req_q <= 1'b1;
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end
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end
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end
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else
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sample_req_q <= 1'b0;
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end
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//-----------------------------------------------------------------
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// I2S DAC Interface
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//-----------------------------------------------------------------
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assign i2s_mclk_o = mclk_q;
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assign i2s_ws_o = ws_q;
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assign i2s_bclk_o = bclk_q;
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assign i2s_data_o = data_q;
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assign sample_req_o = sample_req_q;
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endmodule

‎i2s/testbench/i2s_decoder.cpp

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#include "i2s_decoder.h"
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//-----------------------------------------------------------------
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// input: Handle rx data
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//-----------------------------------------------------------------
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void i2s_decoder::input(void)
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{
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do
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{
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wait();
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}
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while (rst_i.read());
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bool first = true;
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int bit_cnt = 0;
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sc_uint <I2S_MAX_BITS> data = 0;
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sc_uint <I2S_MAX_BITS> rev_data = 0;
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bool ws;
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while (true)
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{
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if (!first)
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{
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// Left
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if (!ws)
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{
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sc_assert(bit_cnt < m_bits);
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rev_data[bit_cnt] = i2s_data_i.read();
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if (++bit_cnt == m_bits)
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{
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for (int i=0;i<m_bits;i++)
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data[m_bits-i-1] = rev_data[i];
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m_rx_fifo.write(data);
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data = 0;
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}
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}
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// Right
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else
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{
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sc_assert(bit_cnt >= m_bits);
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sc_assert(bit_cnt < (m_bits*2));
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rev_data[bit_cnt-m_bits] = i2s_data_i.read();
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if (++bit_cnt == (m_bits*2))
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{
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for (int i=0;i<m_bits;i++)
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data[m_bits-i-1] = rev_data[i];
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m_rx_fifo.write(data);
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data = 0;
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bit_cnt = 0;
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}
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}
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}
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else
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first = false;
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ws = i2s_ws_i.read();
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wait();
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}
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}

‎i2s/testbench/i2s_decoder.h

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#ifndef I2S_DECODER_H
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#define I2S_DECODER_H
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#include <systemc.h>
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#define I2S_MAX_BITS 24
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//-------------------------------------------------------------
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// i2s_decoder: Decoder for I2S interface
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//-------------------------------------------------------------
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SC_MODULE (i2s_decoder)
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{
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public:
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// Clock and Reset
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sc_in <bool> clk_i;
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sc_in <bool> rst_i;
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// I/O
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sc_in <bool> i2s_mclk_i;
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sc_in <bool> i2s_bclk_i;
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sc_in <bool> i2s_ws_i;
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sc_in <bool> i2s_data_i;
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// Constructor
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SC_HAS_PROCESS(i2s_decoder);
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i2s_decoder(sc_module_name name): sc_module(name),
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m_rx_fifo(1024)
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{
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m_bits = 16;
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SC_CTHREAD(input, i2s_bclk_i.pos());
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}
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public:
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sc_uint <I2S_MAX_BITS> read(void) { return m_rx_fifo.read(); }
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bool read_ready(void) { return m_rx_fifo.num_available() > 0; }
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void set_bit_width(int bits) { m_bits = bits; }
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private:
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void input(void);
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sc_fifo < sc_uint<I2S_MAX_BITS> > m_rx_fifo;
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int m_bits;
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};
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#endif

‎i2s/testbench/i2s_driver.cpp

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#include "i2s_driver.h"
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//-----------------------------------------------------------------
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// output: Drive tx data
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//-----------------------------------------------------------------
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void i2s_driver::output(void)
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{
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wait();
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sc_assert(m_tx_fifo.num_available() > 0);
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while (true)
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{
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sample_data_o.write(m_tx_fifo.read());
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wait();
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while (!sample_req_i.read())
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wait();
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}
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}

‎i2s/testbench/i2s_driver.h

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#ifndef I2S_DRIVER_H
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#define I2S_DRIVER_H
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#include <systemc.h>
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//-------------------------------------------------------------
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// i2s_driver:
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//-------------------------------------------------------------
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SC_MODULE (i2s_driver)
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{
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public:
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// Clock and Reset
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sc_in <bool> clk_i;
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sc_in <bool> rst_i;
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// I/O
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sc_in <bool> sample_req_i;
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sc_out <sc_uint<32> > sample_data_o;
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// Constructor
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SC_HAS_PROCESS(i2s_driver);
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i2s_driver(sc_module_name name): sc_module(name),
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m_tx_fifo(2048)
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{
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SC_CTHREAD(output, clk_i.pos());
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}
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public:
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void write(sc_uint <32> data) { m_tx_fifo.write(data); }
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bool write_empty(void) { return m_tx_fifo.num_available() == 0; }
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private:
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void output(void);
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sc_fifo < sc_uint<32> > m_tx_fifo;
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};
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#endif

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