Add interrupt controller

Author: ultraembedded

README.md

@@ -11,6 +11,7 @@ Github:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedd
 | dbg_bridge | UART -> AXI4 Debug Bridge |
 | ftdi_async_bridge | FTDI Asynchronous FIFO Interface |
 | i2s | I2S Master |
+| irq_ctrl | Simple Linux support interrupt controller |
 | sdram | Simple SDRAM Controller |
 | spdif | SPDIF Transmitter |
 | spilite_axi4l | SPI-Lite SPI Master Interface |

irq_ctrl/README.md

@@ -0,0 +1,21 @@
+### AXI Interrupt Controller
+
+Github:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/irq_ctrl)
+
+This component is a simple IRQ controller implementation with AXI4-Lite slave interface.
+The register interface has limited compatibility with Xilinx's LogiCORE IP AXI Interrupt Controller(INTC) IP, enough so that the Linux Kernel driver works with it unmodified.
+
+##### Features
+* 8 interrupt inputs.
+* AXI4-L register interface.
+* Single interrupt output
+
+##### Limitations
+* Active high interrupts only
+* AXI4-L address and data must arrive in the same cycle.
+
+##### Testing
+Verified under simulation and then tested on FPGA using the stock Linux Kernel 4.19 driver (irq-xilinx-intc.c).
+
+##### References
+* [LogiCORE IP AXI Interrupt Controller (INTC) (v4.1)](https://www.xilinx.com/support/documentation/ip_documentation/axi_intc/v4_1/pg099-axi-intc.pdf)