my RISC_CPU is influenced from https://github.com/geekpradd/RISC-CPU-VHDL/tree/main and debugged by claude ai...implemented on vs-code in linux using ghdl and gtkwave.It has a working ALU with sub,add,and nand components other than that it has a working RAM and multiple registers as per
RISC architecture.the wave given below is my output/observation
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16 bit cpu in vhdl
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