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[SYCL][E2E] Disable fill_any_size.cpp on FPGA #12867

[SYCL][E2E] Disable fill_any_size.cpp on FPGA

[SYCL][E2E] Disable fill_any_size.cpp on FPGA #12867

Triggered via pull request January 10, 2025 16:09
@sarnexsarnex
synchronize #16590
sarnex:fill
Status Success
Total duration 57m 41s
Artifacts 1
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sycl-windows-precommit.yml

on: pull_request
detect_changes  /  Decide which tests could be affected by the changes
6s
detect_changes / Decide which tests could be affected by the changes
e2e  /  Intel GEN12 Graphics with Level Zero
42m 20s
e2e / Intel GEN12 Graphics with Level Zero
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Name Size Digest
sycl_windows_default Expired
580 MB
sha256:b7f9dcf6d5560c695bad7f55370dc54b01dec715a69be8a2ec133bb31411b01b